Data Acquisition

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7.9 Stand-alone logger/controllers vs internal systemsLogger/controllers enjoy the same benefits of distributed I/O in that they are modular andcan be located where they are required. Future expansion is easily catered to byincreasing the number of devices in the network.As well as the ability to make decisions remotely, the use of stand-alonelogger/controllers increases system reliability. This is because the stand-alone ordistributed system can continue to operate even when the host computer is not connectedor functional. It also increases overall system performance, by distributing the controldecisions, algorithms and other analysis functions to localized processors.The analog inputs of plug-in data acquisition boards are typically designed to acceptvoltage signals. Where the signal levels are small, or the sensors do not output voltagesignals, or are remotely located from the PC and affected by noise, then some form ofexternal signal conditioning is required. Unlike distributed I/O, logger/controllerstypically have more than one channel per unit, and each one of these channels can beconfigured for operation with a variety of sensors and signals, not just one type of sensorfor one channel. Whilst stand-alone devices do not necessarily have inbuilt filters, theseare most often not required since the units can be located very close to the signal sourceand therefore not as susceptible to noise. In addition, statistical sampling methods, suchas averaging a number of measurements or integrating over the noise cycle, help toeliminate cyclical noise such as mains hum.As stand-alone loggers/controllers can be placed near the signal source and do notnecessarily have to be connected to the host PC, the requirement for lengthy cabling,which can be affected by noise, is greatly reduced.A final advantage is that logger/controllers often include a local operator interface,providing feedback on a system or process at the location of the device.When connected to the host PC, irrespective of whether there is a single logger/controlleror a network of devices, all communications must proceed via the RS-232 interface. Thespeed at which data can be transmitted to and from the logger/controller(s) is limited bythe speed at which data can be transferred across the single RS-232 communications path.This is an important consideration where a number of units send information to be loggedby the host PC or there is a large amount of data to be uploaded. In either case, thenumber of samples that can be taken from each logger/controller is limited by the totalamount of information that can be sent via the communications interface.Unlike specialized high-speed plug-in DAQ boards, stand-alone logger/controllers arenot designed for the sampling of high frequency signals. Logger/controllers do not enjoythe benefits of high-speed microprocessors, high-speed data bus and fast memory storagefacilities such as DMA that characterize modern PCs. Instead, these devices are poweredby local, dedicated microprocessors or microcontrollers. The microprocessor not onlyperforms many tasks associated with the operation of the hardware in the device butpossibly multiple data acquisition and control tasks associated with the program they arerequired to execute. This necessarily means that when operating at full capacity theseloggers/controllers can only sample signals at a very low sampling rate and are thereforemore suited to applications where the signals change more slowly.A final limiting factor, especially where the logger/controller is operating in stand-alonemode, is that the device has a limited amount of memory. The greater the number of
channels and the faster the sampling rate on each channel, the greater the number ofsamples that will be taken in a given time period. In time, the memory will become full.Care must be taken to keep the sampling rate of each channel to the minimum necessary,while still obtaining the information required.Plug-in data acquisition boards can continuously sample data and transfer it directly tothe PC’s memory. Where even greater storage capacity is required, or the data is to bestored permanently, it can be transferred to the hard disk.
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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50 mRS-232 Communication InterfaceS
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speeds are of the order of 1 Mbyte/
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14 Practical Data Acquisition for I
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3PC based data acquisition (DAQ) sy
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3.2.3 FilteringIsolation performs s
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The transfer characteristics of a p
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Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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A/D board can divide the input rang
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a) DC alias caused by sampling at h
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Figure 5.15Frequency spectrum of or
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ate be a minimum of about five time
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Figure 5.20Many aliases combined wi
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initiated. The data is subsequently
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Figure 5.22Time skew between channe
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For each burst trigger, the A/D boa
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Analog output D/A boardsUnlike high
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Like the weighted-current source ne
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The generation of high frequency si
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• The plug-in connector, which pr
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Latched digital I/OFor applications
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y increasing the resistance of R x
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One advantage of this type of relay
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Figure 5.36Waveforms showing genera
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When a counter is configured to ena
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6The standardization of the RS-232
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A duplex system is designed for sen
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Some examples of the HEX and BIN va
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Page 206 and 207: • Pin 7: Signal ground (common)Th
Page 208 and 209: 6.2.5 Examples of RS-232 interfaces
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Page 212 and 213: Another commonly used technique, ba
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Page 216 and 217: The calculation of the block checks
Page 218 and 219: The mechanism of operation of the C
Page 220 and 221: Figure 6.18, has appropriate intern
Page 222 and 223: 77.1 IntroductionAs with other form
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Page 226 and 227: How frequently logged data is uploa
Page 228 and 229: The following hardware components d
Page 230 and 231: In a typical stand-alone data acqui
Page 232 and 233: The maximum battery life that can b
Page 234 and 235: Input termination resistors, typica
Page 236 and 237: Figure 7.13 shows the standard conn
Page 238 and 239: interface, even at high speed, the
Page 240 and 241: • Use different data formats so t
Page 242 and 243: Command errors are reported immedia
Page 244 and 245: • Channel scalingThis automatical
Page 246 and 247: The channel scan for this type of s
Page 248 and 249: Data is logged in a fixed non-ASCII
Page 252 and 253: 88.1 IntroductionThe communications
Page 254 and 255: Figure 8.2GPIB connector (IEEE 488)
Page 256 and 257: • TalkersA talker is a one-way co
Page 258 and 259: controller in charge (CIC). The IFC
Page 260 and 261: Each device connected to the GPIB h
Page 262 and 263: One of the additional features that
Page 264 and 265: • The controller temporarily conf
Page 266 and 267: Table 8.4IEEE 488.2 commandsThe SCP
Page 268 and 269: Figure 8.9SCPI instrument modelThe
Page 270 and 271: 99.1 Ethernet and fieldbuses for da
Page 272 and 273: cabling tray etc and the transceive
Page 274 and 275: transceiver in the MAU and this is
Page 276 and 277: Advantages of the system include:
Page 278 and 279: of a cell as well, but these are ig
Page 280 and 281: Figure 9.8CSMA/CD collisionsAssume
Page 282 and 283: • PreambleThis field consists of
Page 284 and 285: of this figure. Some manufacturers
Page 286 and 287: Grounding has safety and noise conn
Page 288 and 289: Just as with any technology, each o
Page 290 and 291: information. The packet is then pla
Page 292 and 293: There are two types of connectors,
Page 294 and 295: HOSTClient SoftwareManages Interfac
Page 296 and 297: Figure 10.6USB connector pinsThere
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The interrupt transfer type is used
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than in spending a lot of time and
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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