Data Acquisition

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The idle states for low- and high-speed devices are opposite of each other. For the lowspeeddevice the idle state is the D+ line at 0 volts, and the D– a positive voltage. The idlestate for a high-speed device is such that the D+ is a positive voltage and the D– is0 volts. In most data communications, a positive voltage indicates a zero (0) condition,and a one (1), a minus voltage. In the USB system it is not possible to say this because ituses an encoding system called NRZI.The voltages used for differential balanced signaling are:• Maximum voltage transmitted +3.6 V DC• Minimum voltage transmitted +2.8 V DC• Minimum voltage needed to sense a transition +/– 2 V DC• Typical line voltage as seen from the receiver +/– 3 V DCFigure 10.8NRZI exampleThe USB uses non-return to zero inverted (NRZI) encoding scheme. In NRZI, a ‘1’ isdefined as ‘no change’ or ‘transition’ of voltage whereas a ‘0’ is a change or transition ofvoltage. A string of ‘0s’ would cause a clock-like data stream. The USB signaling systemuses the transition from one voltage to another to synchronize the receivers. A stream ofones therefore would mean no transitions. This would cause the receiver to losesynchronization. To overcome this problem the USB system uses a 6 of 7 bit stuffingtechnique. If six or more ones are to be transmitted in a row the transmitter stuffs in azero (a transition). If the receiver sees six ones in a row, it knows that the next transition(zero) is to be ignored.Devices like keyboards and mice need power to operate. This power is supplied by theUSB system through the cables and hubs. External hubs can be either self-powered orpowered off the bus. The voltage supplied by a USB hub is +5 V DC. The hubs must beable to supply a minimum of 100 mA and a maximum of 500 mA, through each port. Ifan external hub with four ports is powered off the bus, then it will divide the 500 mAsupplied between the ports. Four times 100 mA equals 400 mA. This leaves 100 mA to
un the hub. It is not possible to connect two bus-powered hubs together unless thedevices connected to the last hub were self-powered. If the external hub is self powered,that is mains powered, it should be able to supply 500 mA to each of the ports.10.4 <strong>Data</strong> link layerThe data link layer within the USB specification defines the USB as a master/slave, halfduplex, timed communication bus system, designed to connect close peripherals andexternal hubs. The hardware and software devices such as the host hub controllerhardware and driver, USB software driver and device drivers all contribute to the datalink layer of the USB.All these devices working together accomplish the following:• Collects data off the PCI bus via the device drivers• Processes the information or data• Verifies, determines and processes the different transfer types• Calculates and checks for errors in the packets and frames• Puts the different packets into a 1 ms frame• Checks for start of frame delimiters• Sends the packets to the physical layer• Receives packets from the physical layer Table 10.1USB data link layer block diagramA good place to start when looking at the data link layer of the USB is at the fourdifferent transfer types. The wide range of devices that the USB has to deal with requirethat there be multiple transfer types.These are:• Interrupt transfer• Isochronous transfer• Control transfers• Bulk transfersAs stated before, there are two speeds that can be used in the USB system. For the mostpart the data link layer is the same, but there are some differences. The low speed devicesdo not support bulk and isochronous transfers. The reason for this will become apparentin the following transfer descriptions.
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Practical Data Acquisition forInstr
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Practical Data Acquisition forInstr
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In less than a decade, the PC has b
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PrefaceContentsxvii1 Introduction 1
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Contents vii4.2.1 Hardware interrup
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Contents ix6.2.3 Functional descrip
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Contents xi9.1 Ethernet and fieldbu
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Contents xiii12.5.2 Pin assignments
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Contents xvType R thermocouple 384T
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A data acquisition and control syst
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FilteringIn noisy environments, it
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are capable of programmed I/O and i
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Plug-in expansion boards are common
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50 mRS-232 Communication InterfaceS
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speeds are of the order of 1 Mbyte/
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14 Practical Data Acquisition for I
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3PC based data acquisition (DAQ) sy
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3.2.3 FilteringIsolation performs s
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The transfer characteristics of a p
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Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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A/D board can divide the input rang
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a) DC alias caused by sampling at h
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Figure 5.15Frequency spectrum of or
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ate be a minimum of about five time
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Figure 5.20Many aliases combined wi
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initiated. The data is subsequently
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Figure 5.22Time skew between channe
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For each burst trigger, the A/D boa
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Analog output D/A boardsUnlike high
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Like the weighted-current source ne
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The generation of high frequency si
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• The plug-in connector, which pr
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Latched digital I/OFor applications
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y increasing the resistance of R x
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One advantage of this type of relay
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Figure 5.36Waveforms showing genera
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When a counter is configured to ena
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6The standardization of the RS-232
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A duplex system is designed for sen
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Some examples of the HEX and BIN va
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In summary, the optional settings f
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At the RS-232 receiver the followin
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110 850300 800600 7001200 5002400 2
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• Pin 7: Signal ground (common)Th
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6.2.5 Examples of RS-232 interfaces
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terminating resistors, approximatel
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Another commonly used technique, ba
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• Line controlThis applies to hal
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The calculation of the block checks
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The mechanism of operation of the C
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Figure 6.18, has appropriate intern
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77.1 IntroductionAs with other form
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inserted in the device. This is its
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How frequently logged data is uploa
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The following hardware components d
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In a typical stand-alone data acqui
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The maximum battery life that can b
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Input termination resistors, typica
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Figure 7.13 shows the standard conn
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interface, even at high speed, the
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• Use different data formats so t
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Command errors are reported immedia
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• Channel scalingThis automatical
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The channel scan for this type of s
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Page 250 and 251: 7.9 Stand-alone logger/controllers
Page 252 and 253: 88.1 IntroductionThe communications
Page 254 and 255: Figure 8.2GPIB connector (IEEE 488)
Page 256 and 257: • TalkersA talker is a one-way co
Page 258 and 259: controller in charge (CIC). The IFC
Page 260 and 261: Each device connected to the GPIB h
Page 262 and 263: One of the additional features that
Page 264 and 265: • The controller temporarily conf
Page 266 and 267: Table 8.4IEEE 488.2 commandsThe SCP
Page 268 and 269: Figure 8.9SCPI instrument modelThe
Page 270 and 271: 99.1 Ethernet and fieldbuses for da
Page 272 and 273: cabling tray etc and the transceive
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Page 278 and 279: of a cell as well, but these are ig
Page 280 and 281: Figure 9.8CSMA/CD collisionsAssume
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Page 288 and 289: Just as with any technology, each o
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Page 294 and 295: HOSTClient SoftwareManages Interfac
Page 296 and 297: Figure 10.6USB connector pinsThere
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Page 316 and 317: Size 85.6 mm × 54.0 mmType I 3.3 m
Page 318 and 319: The memory only interface is conver
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Page 322 and 323: 12.8 FutureThe card information str
Page 324 and 325: A/D conversion timeAddressAddress r
Page 326 and 327: Back-planeBand pass filterBandwidth
Page 328 and 329: BufferBusBWCache memoryCCDCCIRCCITT
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Page 334 and 335: FrameFrame grabberFringingFull dupl
Page 336 and 337: so that they interlock. The PAL sta
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Page 340 and 341: NTSCNull modemNumber of channelsNyq
Page 342 and 343: PortPPIPre-triggerProgram I/OProgra
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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