Data Acquisition

4.2.7 Interrupt service routinesIt does this by saving the current code segment instruction pointer (CS:IP) andsystem FLAGS registers onto the stack.It is important to note that at this time the interrupt enable flag bit IF of the CPUFLAGS register is also cleared, disabling further interrupts.The CPU finally fetches the instruction pointer (IP) and code segment (CS)value from the interrupt vector table at the correct location for the interrupt beingserviced, and branches to this address.It should be noted that the CPU assumes that the address retrieved is in fact thestarting address of a valid ISR. If it is not, then the CPU begins executing at thisaddress anyway and will probably never return, causing the program being executedwhen the interrupt occurred to appear ‘locked up’ or, even worse, to malfunction,with potentially dangerous consequences. Due to the possible severity ofthis error, it is important to correctly initialize the interrupt vector routine for theinterrupt service required (see Initialization required for interrupts, p. 74).Apart from the function(s) that are expected to be performed by the ISR and the reason it wasrequested in the first place, there are several other considerations and certainly some importanttasks that must be performed within the ISR.These are listed below:• Any CPU registers that might be used by the ISR, (registers that the interruptedprogram could have been using), should be saved by pushing their current valuesonto the stack. Only those registers whose values will be altered need be saved,although it is safe programming practice to save all registers (remember that theCS, IP and FLAGS registers are automatically saved by the CPU).• Since the interrupt enable flag bit IF in the FLAGS register has been cleared andinterrupts to the CPU are disabled, a decision must be made whether to set thisflag bit and re-enable INTR interrupts to the CPU. If this is the case higher levelinterrupts may interrupt the current ISR. Although this may be required, theconsequences of allowing this must be considered carefully.Note that even when interrupt requests from the master PIC to the CPU aredisabled, interrupts may still be received by the PIC(s) and will remain pendinguntil serviced.The interrupt request latch on the I/O device requesting service must be reset sothat further interrupts can be received from the same device.It is usual practice (but strictly dependent on the hardware of the expansionboard) that resetting the interrupt request latch will leave the IRQ line disabled orin a high impedance tri-state.Pull up resistors on the system board are used to take the IRQx signal lines to a5 V logic level when not in use and, when floated, are guaranteed to be high after500 ns. This means that the ISR must reset the I/O devices interrupt latch at least500 ns before issuing an end of interrupt (EOI) command to the PIC(s) (seebelow).This must be strictly observed to avoid the possibility of an unknown transitionof the IRQ line from low to high in the high impedance state, inadvertentlytriggering an interrupt on the IRQ signal line.• An EOI command must be sent to the master PIC to re-enable interrupts on thesame IRQ line. Where an interrupt occurred on one of the interrupt lines IRQ8–IRQ15 via the slave PIC an EOI command must be sent to this PIC as well.