Data Acquisition

DMA cycles, data is transferred directly from the I/O device to memory (or vice versa) on thedata lines while the processor is disconnected from them. The DMA controller drives thecontrol lines in this case. Bus masters may also take control of these lines.D[15..8]D[15..8] are the high eight bits of the 16-bit bi-directional data bus. They are similar to thelower eight data lines, D[7..0]. 8-bit wide transfers must use D[7..O]. If the currently runningsoftware requests a 16-bit transfer from an 8-bit device, the system board automaticallyconverts it into two 8-bit cycles on D[7..O]. Adapters capable of 16-bit transfers mustindicate this using /M16 or /IO16 during cycles addressed to them or the system board willconvert the instruction into two 8-bit instructions. /SBHE (explained later), is asserted by thesystem board during 16-bit cycles.LA[23..17]The LA17 to LA23 (latchable address) lines form part of the latchable address bus. (Theremaining lines of the latchable address bus, LA[16..2] and LA[31..24] are wired to the EISAconnector and are not available in ISA systems. SA[19..0] must be used instead.)LA16 to LA23 are unlatched and, if required for the whole bus cycle, must be latched bythe addressed slave. During standard cycles, they are valid during the active time of theBALE signal (explained later) and remain valid for at least ½ BCLK period after the commandsignals are asserted.During DMA or ISA bus master cycles, LA[23..17] are valid at least one BCLK before thecommand signals are asserted. They may be driven by an expansion board acting as a busmaster. These lines may be latched with the trailing edge of BALE.These address lines are provided in this way because they are pipelined from one cycle tothe next, and to reduce address delay when they are used to decode a block of bus-attachedmemory.SA[19..0]Address lines SA0 through SA19 are used to address system bus I/O and memory devices.They form the low-order 20 bits of the 32-bit address bus. (However, only 24 of the 32address lines are normally available in ISA systems.)On normal cycles SA0 to SA 19 are driven onto the bus while BALE is high and they arelatched by the system board on the trailing edge of BALE and are therefore valid throughoutthe bus command cycle.During DMA and 16-bit ISA bus master cycles, they are driven by the DMA logic and busmaster respectively. They should be valid one BCLK before the command signals andnormally stay valid one BCLK after the command signals end.With 20 address lines it is possible to address 1 MB of memory, but not all addresslocations are available. Base system memory, system ROMs and display memory all useaddresses in this range.The processor, using the IN and OUT instructions, addresses I/O devices with lines SA0through SA15, while SA16 through SA19 are not used and are held inactive. Most PC I/Odevices only decode the first ten address lines, (SA0 to SA9, which correspond to I/Oaddresses 0h to 3FFh) so care must be taken when addressing I/O devices with SA10 toSA15./SBHE/SBHE (system bus high enable) is an output-only signal. When low, it indicates to theexpansion board that the present cycle expects to transfer data on the high half of the D[15..0]