Data Acquisition

Capacitive loadingCapacitive loading of the output bus signals is the capacitance that the signal line drivercircuit sees, and is related to the length of the bus signal lines. As the capacitance is increased(with the addition of further expansion cards), the signal can become distorted and delayed,affecting critical timing conditions for bus signals.Where the capacitive coupling between signal lines is significant, and especially when thesignal lines are being driven at high frequency, then noise or signal chatter between signallines can also affect the timing of bus signal lines and performance of the bus.This is especially true when expansion boxes with a long connection to the PC are fittedand there are many cards installed.A common engineering practice by manufacturers is to deliberately limit the length of thesebus signal lines on expansion cards.Bus bandwidth is the maximum frequency at which data can be reliably transmitted on thebus. This is related to the transmission line characteristics of each of the bus signal lines, thecapacitive loading on each signal line and the capacitive coupling between them.Although the manufacture of a multitude of IBM clones has meant that bus characteristicscan vary between manufacturers, a common maximum transmission rate (bus bandwidth) is100 MHz.Bus loadingThe simple and safe rule here is that the maximum loading presented to any bus signal lineshould not exceed more than 2 LS TTL devices.Power supply (VCC) noiseThe frequency of noise that may appear on the power supply is directly related to thefrequency that an IC changes state, since the power that ICs draw from the power supplychanges as they change state.By decoupling each IC device on the board from its power supply with a 0.1 uF ceramiccapacitor, the noise being applied back to the supply is greatly reduced. If this power supplynoise is not decoupled, then the high frequency power supply changes can be induced intoother ICs and also capacitively coupled to other important bus signal lines, possibly affectingthe correct operation of the expansion bus.4.10.2 Address decodingI/O devices addressed within the memory or I/O address map of the PC must be uniquelyaddressable and must not conflict with other memory or I/O addresses in the system.The base address of an I/O device determines where in the computer’s memory or I/Oaddress space the computer will find the I/O device and represents the ‘lowest’ address thatwill access this device. This setting must be unique for all I/O devices in the computer andcannot lie within an addressable range of any other I/O device. Memory or I/O locations onI/O devices are usually addressed in a linear range, from the base address up.The I/O device must correctly decode the address signals, allowing access for only theproper addresses. This is usually performed by a dip switch located on the I/O device.The unused locations in the PC’s I/O map are dependent on the type of computer used(PC/XT/AT).It is up to the user to find an unused area in the PC’s I/O address space, taking into accountthe addresses of all other installed I/O devices.To allow greater flexibility, it is common practice for the base address of an I/O device tobe settable within a large range of I/O addresses.