Data Acquisition

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Contents ix6.2.3 Functional description of the interchange circuits 1876.2.4 The sequence of operation of the EIA-232 interface 1886.2.5 Examples of RS-232 interfaces 1906.2.6 Main features of the RS-232 Interface Standard 1906.3 RS-485 interface standard 1916.3.1 RS-485 repeaters 1926.4 Comparison of the RS-232 and RS-485 standards 1936.5 The 20 mA current loop 1946.6 Serial interface converters 1946.7 Protocols 1956 7.1 Flow control protocols 1966.7.2 ASCII-based protocols 1966.8 Error detection 1986.8.1 Character redundancy checks 1996.8.2 Block redundancy checks 1996.8.3 Cyclic redundancy Checks 1996.9 Troubleshooting & testing serial data communication circuits 2006.9.1 The breakout box 2016.9.2 Null modem 2016.9.3 Loop back plug 2026.9.4 Protocol analyzer 2026.9.5 The PC as a protocol analyzer 2027 Distributed and stand-alone loggers/controllers 2047.1 Introduction 2047.2 Methods of operation 2047.2.1 Programming and logging data using PCMCIA cards 2057.2.2 Stand-alone operation 2067.2.3 Direct connection to the host PC 2067.2.4 Remote connection to the host PC 2087.3 Stand-alone logger/controller hardware 2097.3.1 Microprocessors 2107.3.2 Memory 2107.3.3 Real time clock 2117.3.4 Universal asynchronous receiver/transmitter (UART) 2127.3.5 Power supply 2137.3.6 Power management circuitry 2147.3.7 Analog inputs and digital I/O 2157.3.8 Expansion modules 2177.4 Communications hardware interface 2177.4.1 RS-232 interface 2177.4.2 RS-485 standard 2197.4.3 Communication bottlenecks and system performance 2197.4.4 Using Ethernet to connect data loggers 2207.5 Stand-alone logger/controller firmware 220
x Contents7.6 Stand-alone logger/controller software design 2217.6.1 ASCII based command formats 2227.6.2 ASCII based data formats 2237.6.3 Error reporting 2237.6.4 System commands 2247.6.5 Channel commands 2247.6.6 Schedules 2267.6.7 Alarms 2297.6.8 <strong>Data</strong> logging and retrieval 2297.7 Host software 2307.8 Considerations in using standalone logger/controllers 2317.9 Stand-alone logger/controllers vs internal systems 2327.9.1 Advantages 2327.9.2 Disadvantages 2328 IEEE 488 Standard 2348.1 Introduction 2348.2 Electrical and mechanical characteristics 2358.3 Physical connection configurations 2368.4 Device types 2378.5 Bus structure 2388.5.1 <strong>Data</strong> lines 2398.5.2 Interface management lines 2398.5.3 Handshake lines 2408.6 GPIB handshaking 2408.7 Device communication 2418.7.1 GPIB addressing 2428.7.2 Un-addressing devices 2428.7.3 Terminating data messages 2428.7.4 Sending and receiving data 2438.8 IEEE 488.2 2438.8.1 Requirements of IEEE 488.2 controllers 2438.8.2 IEEE 488.2 control sequences 2448.8.3 IEEE 488.2 protocols 2448.8.4 Device interface capabilities 2468.8.5 Status reporting model 2468.8.6 Common command set 2478.9 Standard commands for programmable instruments (SCPI) 2488.9.1 IEEE 488.2 common commands required by the SCPI 2488.9.2 SCPI required commands 2498.9.3 The SCPI programming command model 2498.9.4 SCPI hierarchical command structure 2519 Ethernet & LAN systems 252
Page 2 and 3: Practical Data Acquisition forInstr
Page 4 and 5: Practical Data Acquisition forInstr
Page 6 and 7: In less than a decade, the PC has b
Page 8 and 9: PrefaceContentsxvii1 Introduction 1
Page 10 and 11: Contents vii4.2.1 Hardware interrup
Page 14 and 15: Contents xi9.1 Ethernet and fieldbu
Page 16 and 17: Contents xiii12.5.2 Pin assignments
Page 18 and 19: Contents xvType R thermocouple 384T
Page 20 and 21: A data acquisition and control syst
Page 22 and 23: FilteringIn noisy environments, it
Page 24 and 25: are capable of programmed I/O and i
Page 26 and 27: Plug-in expansion boards are common
Page 28 and 29: 50 mRS-232 Communication InterfaceS
Page 30 and 31: speeds are of the order of 1 Mbyte/
Page 32 and 33: 14 Practical Data Acquisition for I
Page 54 and 55: 3PC based data acquisition (DAQ) sy
Page 56 and 57: 3.2.3 FilteringIsolation performs s
Page 58 and 59: The transfer characteristics of a p
Page 60 and 61: Figure 3.7Ideal band pass filter tr
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Figure 3.11Two-stage Butterworth fi
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As individual signal conditioning m
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ThermocouplesDigitalTransmitterDigi
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Examples of floating signal sources
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espect to the measurement system gr
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Figure 3.26Opto-coupler isolation o
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• Using isolation amplifiers to i
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Figure 3.31Physical representation
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field or if the field is caused by
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Where the shield is grounded (i.e.
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mines the amount of noise in the ci
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For full-duplex systems using balan
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4.1.1 DOSusually consist of a small
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With the advent of Windows as a gra
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UNIX shellSimilar to the DOS comman
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available to the expansion bus. A l
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4.2.7 Interrupt service routinesIt
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Whichever CPU is being used, it mus
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• An I/O device requests a DMA tr
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Normal DMA using on-board FIFOThe D
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ferring samples until the counter r
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The read or write command signals (
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Shortened 3-BCLK 8-bit memory acces
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Extended 6-BCLK 16-bit memory acces
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• A cycle which the expansion boa
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Figure 4.13Timing chart of a shorte
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Figure 4.15Timing chart of an exten
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4.7.2 Expanded memory system (EMS)E
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The IBM PC and early versions of th
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Figure 4.17ISA signal mnemonics, si
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data bus. An example of this happen
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NOWSThe /NOWS (NO wait state) signa
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interrupt lines (1RQ13, 8, 2, 1 and
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one application at a time, it is ne
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The need for PCs to exchange data w
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Figure 4.198-bit 21-line I/O board4
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Address decoding on the 24-line pro
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The write cycle is considered in th
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data acquisition and control system
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Adjustable on-board fixed gain ampl
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level applied at the input. When a
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Each step effectively divides the r
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The operation of a dual slope integ
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Code widthThis is the fundamental q
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(a) Unipolar offset error(b) Bipola
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Changes in temperature result in a
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1 LSB. Therefore, an ideal A/D conv
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• The source and level of interru
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5.3.3 Differential inputsTrue diffe
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A/D board can divide the input rang
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a) DC alias caused by sampling at h
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Figure 5.15Frequency spectrum of or
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ate be a minimum of about five time
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Figure 5.20Many aliases combined wi
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initiated. The data is subsequently
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Figure 5.22Time skew between channe
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For each burst trigger, the A/D boa
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Analog output D/A boardsUnlike high
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Like the weighted-current source ne
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The generation of high frequency si
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• The plug-in connector, which pr
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Latched digital I/OFor applications
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y increasing the resistance of R x
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One advantage of this type of relay
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Figure 5.36Waveforms showing genera
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When a counter is configured to ena
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6The standardization of the RS-232
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A duplex system is designed for sen
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Some examples of the HEX and BIN va
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In summary, the optional settings f
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At the RS-232 receiver the followin
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110 850300 800600 7001200 5002400 2
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• Pin 7: Signal ground (common)Th
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6.2.5 Examples of RS-232 interfaces
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terminating resistors, approximatel
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Another commonly used technique, ba
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• Line controlThis applies to hal
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The calculation of the block checks
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The mechanism of operation of the C
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Figure 6.18, has appropriate intern
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77.1 IntroductionAs with other form
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inserted in the device. This is its
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How frequently logged data is uploa
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The following hardware components d
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In a typical stand-alone data acqui
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The maximum battery life that can b
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Input termination resistors, typica
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Figure 7.13 shows the standard conn
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interface, even at high speed, the
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• Use different data formats so t
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Command errors are reported immedia
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• Channel scalingThis automatical
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The channel scan for this type of s
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Data is logged in a fixed non-ASCII
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7.9 Stand-alone logger/controllers
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88.1 IntroductionThe communications
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Figure 8.2GPIB connector (IEEE 488)
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• TalkersA talker is a one-way co
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controller in charge (CIC). The IFC
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Each device connected to the GPIB h
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One of the additional features that
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• The controller temporarily conf
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Table 8.4IEEE 488.2 commandsThe SCP
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Figure 8.9SCPI instrument modelThe
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99.1 Ethernet and fieldbuses for da
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cabling tray etc and the transceive
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transceiver in the MAU and this is
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Advantages of the system include:
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of a cell as well, but these are ig
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Figure 9.8CSMA/CD collisionsAssume
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• PreambleThis field consists of
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of this figure. Some manufacturers
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Grounding has safety and noise conn
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Just as with any technology, each o
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information. The packet is then pla
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There are two types of connectors,
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HOSTClient SoftwareManages Interfac
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Figure 10.6USB connector pinsThere
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The idle states for low- and high-s
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The interrupt transfer type is used
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than in spending a lot of time and
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• The sensitivity of the output/i
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term error (m) in the system and ad
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11.2 Capturing high speed transient
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12IntroductionThe PCMCIA (PCMCIA st
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adapter on a full size computer has
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Pager cards are used in offices and
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Size 85.6 mm × 54.0 mmType I 3.3 m
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The memory only interface is conver
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The AIMS interface supports large d
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12.8 FutureThe card information str
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A/D conversion timeAddressAddress r
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Back-planeBand pass filterBandwidth
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BufferBusBWCache memoryCCDCCIRCCITT
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pixel is subjected to a mathematica
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data between the computer memory an
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FrameFrame grabberFringingFull dupl
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so that they interlock. The PAL sta
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Lux-secondSI unit of light exposure
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NTSCNull modemNumber of channelsNyq
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PortPPIPre-triggerProgram I/OProgra
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whereby the first gray level of eac
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allowing the user to control basic
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input.TrunkUARTUnipolar inputsUnloa
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Appendix BThe information in this s
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Table B.4Controller 2: 16-bit (AT o
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B.5 8253/8254 Counter/timer
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Table B.8Memory map for PC/XT/AT
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Table B.10BIOS data area
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Table B.15ROMTable B.16AT extended
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← ↔ ← ← ← ↔
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Figure B.1Card dimensions for PC/XT
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Appendix CThis section contains bri
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the control register of the 8255. T
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The bits A7 (MSB) down to A0 (LSB)
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Table C.6Instructions for reading o
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The program could also enable the I
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Group AConfiguration Informationto
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C.11 Single-bit set/resetAny of the
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Figure C.15Bi-directional bus (mode
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Figure D.18254 Block diagramFigure
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Figure D.3TCCTRL registerThe functi
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This is the data register of the fi
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• A simple read operation• A co
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The null count bit indicates if the
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For even counts: the output is init
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Appendix EThe IPTS-68 standard defi
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Number of ranges = 2Range #1 -270 t
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Range #2 0 to 1372°COrder of polyn
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Number of Ranges = 4Range #1 -50 to
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Appendix FF.1 IntroductionAll activ
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Table F.3 gives the conversion betw
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The conversion between binary and h
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F.8 Internal representation of info
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12 which is equivalent to: 1100-4 S
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DCDCASDCISDCLDDDIODTDTASDTISENDEOIE
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STBSTRSSWNST(T)TETACSTADSTAGTCATCST
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404 IndexDuplex:full duplex 178half
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406 IndexOpen loop control 285see a
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THIS BOOK WAS DEVELOPED BY IDC TECH
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Data Acquisition

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