The Impact of Dennard's Scaling Theory - IEEE

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RESEARCH HIGHLIGHTS for 10-mm Uninterrupted RC-Limited Global On- Chip Interconnects”, IEEE Journal of Solid State Circuits, Vol. 41, No. 1, pp. 297- 306, Jan. 2006. [8] J.H.R. Schrader, E.A.M. Klumperink, J.L. Visschers, B. Nauta, “Pulse-Width Modulation Pre Emphasis applied in a Wireline Transmitter, achieving 33dB Loss Compensation at 5-Gb/s in About the Author Bram Nauta was born in Hengelo, The Netherlands. In 1987 he received the M.Sc degree (cum laude) in electrical engineering from the University of Twente, Enschede, The Netherlands. In 1991 he received the Ph.D. degree from the same university on the subject of analog CMOS filters for very high frequencies. In 1991 he joined the Mixed-Signal Circuits and Systems Department of Philips Research, Eindhoven the Netherlands, where he worked on high speed AD converters and analog key modules. In 1998 he returned to the University of Twente, as full professor heading the IC Design group, which is part of the Corrections continued from page 4 Fig. 4. Photomicrograph of one of the first planar integrated circuits produced by Fairchild Semiconductor in the early 1960’s. The unusual diameter of 764 microns was chosen because we were working in English units and that is thirty thousandths of an inch, or 30mils. The minimum feature size is the three mil metal line making the circular base contact. Metal-tometal spacing is five mils to allow the 2.5mil alignment tolerance we needed. Interestingly enough at the time the idea for the planar transistor was conceived by Jean Hoerni in the early days of Fairchild Semiconductor, it had to sit untried for a couple of years, because we did not have the technology to do four aligned mask layers. In fact, we were developing the technology to do two aligned oxide-masked diffusions plus a mesa etching step for transistors. The original step and repeat camera that Bob Noyce designed using matched 16mm movie camera lenses had only three lenses, so it could only step a three-mask set. We had to wait until the first mesa transistors were in production before we could go back and figure out how to make a four mask set to actually try the planar idea. The first integrated circuit on the graph is one of the first planar integrated circuits produced. It included four transistors and six resistors. 0.13-μm CMOS”, IEEE Journal of Solid-State Circuits, Vol. 41, No. 4, pp.990-999, April 2006. [9] S. Radovanovic, A.J. Annema, B. Nauta, “A 3 Gb/s optical detector in standard CMOS for 850 nm optical communication” IEEE Journal of Solid-State Circuits, Volume 40, No.8, Pg:1706 - 1717, Aug. 2005. CTIT Research Institute. His current research interest is high-speed analog CMOS circuits. Besides, he is also part-time consultant in industry and in 2001 he co-founded Chip Design Works. His Ph.D. thesis was published as a book: Analog CMOS Filters for Very High Frequencies, (Springer, 1993) and he received the “Shell Study Tour Award” for his Ph.D. Work. From 1997-1999 he served as Associate Editor of IEEE Transactions on Circuits and Systems -II; Analog and Digital Signal Processing, and in 1998 he served as Guest Editor for IEEE Journal of Solid-State Circuits. From 2001 to 2006 he was Associate Editor for IEEE Journal of Solid-State Circuits and he is also member of the technical program committees of ISSCC, ESSCIRC, and Symposium on VLSI circuits. He is co-recipient of the ISSCC 2002 “Van Vessem Outstanding Paper Award.” It has always bothered me that the picture of this important device that got preserved was of the ugly chip shown in Fig. 4. The circuit had six bonding pads around the circumference of a circle for mounting in an 8-leaded version of the old TO-5 outline transistor can. In this case only six of the eight possible connections were required. We did not think we could make eight wire bonds with reasonable yield, so for these first integrated circuits we etched a round die that let us utilize blobs of conducting epoxy to make contact to the package pins. For the die in the picture, the etching clearly got away from the etcher. A prior version of “The Mythology of Moore’s Law,” by Tom R. Halfhill in the September 2006 issue was published in Microprocessor Report of December, 2004. 10 IEEE SSCS NEWSLETTER Winter 2007
A 30 Year Retrospective on Dennard’s MOSFET Scaling Paper Mark Bohr, Intel Corporation, mark.bohr@intel.com More than three decades have passed since the team of Robert Dennard, Fritz Gaensslen, Hwa-Nien Yu, V. Leo Rideout, Ernest Bassous and Andre LeBlanc from the IBM T. J. Watson Research Center wrote the seminal paper describing MOSFET scaling rules for obtaining simultaneous improvements in transistor density, switching speed and power dissipation [1]. At the time of this paper (1974), commercially available circuits were using MOSFETs with gate lengths of approximately 5 microns, but devices with shorter gate lengths were already being built in laboratories that were demonstrating the benefits of further scaling. The scaling principles described by Dennard and his team were quickly adopted by the semiconductor industry as the roadmap for providing systematic and predictable transistor improvements. Table I is reproduced from Dennard’s paper and summarizes transistor or circuit parameter changes under ideal scaling conditions, where κ is the unitless scaling constant. The tantalizing benefits of MOSFET device scaling immediately leap out from this table: as transistors get smaller, they can switch faster and use less power. But of course learning exactly how to make transistors smaller in a way that could be done practically in high volume manufacturing would take time. It would take time to develop lithographic techniques to pattern smaller feature sizes, to grow thinner gate oxides, and to reduce defect levels at these increasingly challenging dimensions. But this paper gave our industry a roadmap, a method for setting targets and expectations for coming generations of process technology. This paper gave us the more specific transistor scaling formula needed to continue Moore’s Law, which was first articulated in a paper by Table I: Scaling Results for Circuit Performance (from Dennard) TECHNICAL ARTICLES Gordon Moore in 1965 and was in effect being followed by the semiconductor industry since the early 1960’s. (To read reprints of Gordon Moore’s 1965 and 1975 papers along with recent commentaries on Moore’s Law, see the September 2006 issue of the IEEE Solid-State Circuits Society Newsletter.) The ideas described in Moore’s and Dennard’s papers set our industry on a course of developing new integrated circuit process technologies and products on a regular pace and providing consistent improvements in transistor density, performance and power. Each new generation of process technology was expected to reduce minimum feature size by approximately 0.7x (κ ~1.4). A 0.7x reduction in linear features size was generally considered to be a worthwhile step to take for a new process generation as it provided roughly a 2x increase in transistor density. During the 1970’s and 1980’s the semiconductor industry was introducing new technology generations approximately every 3 years. This translates to transistor density improvements of ~2x every 3 years, but this was also a period when average chip sizes were increasing, resulting in transistor count increases of close to 4x every 3 years (or 2x every 18 months). Starting in the mid-1990’s our industry accelerated the pace of introducing new technology generations to once every 2 years and that pace continues to this day (see Figure 1). The trend of increasing chip size has slowed due to cost constraints, so we have settled into a trend of roughly doubling transistor density and transistor count every 2 years (see Figure 2). Even more surprising, from a MOSFET scaling perspective, is that over the past 10 years MOSFET gate lengths have been scaling faster than other minimum feature sizes (see Figure 1). Prior to the mid-1990’s, Figure 1: Feature size scaling for Intel logic technologies Winter 2007 IEEE SSCS NEWSLETTER 11
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