The Impact of Dennard's Scaling Theory - IEEE

TECHNICAL ARTICLES
Device Scaling: The Treadmill that Fueled Three
Decades of Semiconductor Industry Growth
Pallab Chatterjee, i2 Technologies, Inc.
In 1974 Robert Dennard, etal 1, wrote a paper that
explored different methods of scaling MOS devices,
and pointed out that if voltages were scaled with
lithographic dimensions, one achieved the benefits we
all now assume with scaling: faster, lower energy, and
cheaper gates. The lower energy per switching event
exactly matched the increased energy by having more
gates and having them switch faster, so in theory the
power per unit area would stay constant. This set of linear
scaling principles of MOS technology has served as
the treadmill on which the entire Semiconductor Industry
has grown for the past three decades.
Scaling in the 70’s: The Era of NMOS
Dynamic Random Access Memories
The late 70’s NMOS based DRAMs led the technology
scaling charge in a world that was still largely bipolar and
dominated by TTL logic chips. The first rounds of the
application of scaling theory were focused on DRAMs.
Unique clock design schemes for DRAMs devised at
Mostek and technology from Intel and IBM ushered in
the 16k bit VLSI DRAM, the pride of the late 70’s.
Japan’s MITI created the VLSI Technology Project 2,
a consortium of five top Japanese microelectronics
companies: Hitachi, NEC, Fujitsu, Mitsubishi and
Toshiba. This consortium developed a complete technology
infrastructure for the 256K DRAM and
launched into the 1 micron VLSI era with strong
progress in ultra clean technologies which gave Japan
the lead in VLSI manufacturing in the early 80’s.
The Early 80’s: Crossing the Micron Barrier
Even though the scaling charge was led by NMOS,
power and ease of design considerations favored
CMOS Technology as the industry workhorse. The
world, however, was stuck at the TTL voltage and
logic level standard or 5V. The resistance to scaling
voltage in the early 80’s from system designers backed
into the semiconductor world. This led me to propose
a quasi constant voltage scaling 3.The emergence of
voltage tolerant device structures like the lightly dope
drain (LDD) transistor, silicide clad source drain, and
hot electron defense resulted from this. These technologies
provided some of the keys to continue scaling
feature sizes slower than voltage and continuing
the treadmill for the Semiconductor Industry.
ASIC and CAD Transforms the Chip Design
Industry
Carver Meade and Lynn Conaway in their classic
book, ‘Introduction to VLSI Systems’, used the notion
of linear relationships between different device
geometries to simplify the “design rules” that abstracted
the manufacturing constraints from design. Linear
device scaling theory also allowed simplification of a
very complex interaction of process and device
physics with design.
Device models to represent the complex physics of
CMOS devices in circuit simulators, like SPICE, provided
the abstraction between circuit theory and device
physics. Based on these abstractions the industry was
able to rapidly develop design tools and systems. The
University of California, Berkeley 4 was a leader in developing
a suite of design tools that connected logic level
design to circuit design to physical design and verification
tools to check for design rules. The entire ASIC
world of semi-custom chips opened up based on this set
of abstractions and made scaling applicable to all chips.
The Emergence of TCAD: Systematic
Technology Design
The notion of creating generations of process technology
that could be used for a variety of applications
was emerging simultaneously with the ASIC movement
to systematize chip design. Linear scaling factors
began to be used as the names of the generation of
technology and an informal time table started being
discussed across the industry. A team at Stanford University
initiated a whole new field of technology CAD 5
with Process Simulators and Device Simulators. This
allowed systematic design of process and devices
using formal design of experiment methods.
Manufacturing yield and defect analysis did not come
under the purview of scaling theory and threatened to
stop the scaling treadmill. Redundancy and repair techniques
based on laser links were the initial answer to
continue memory scaling beyond 256 Kbit. This was
followed by yield analysis tools that were developed at
Carnegie Mellon University 6. Defect measurement tools
offered by KLA, systematic yield analysis and ramp
processes made the technology treadmill continue to
move down the linear scaling path.
Single Wafer Manufacturing Systems for
Scaling to Larger Wafers with Sub Half
Micron Features
From 1988 through 1993 Texas Instruments partnered
with DARPA, the U.S. Air Force, semiconductor equipment
makers, and university researchers in the Microelectronics
Manufacturing Science and Technology
(MMST) Program 7. Its purpose was to develop advanced
IC manufacturing technologies enabling dramatic
14 IEEE SSCS NEWSLETTER Winter 2007