The Impact of Dennard's Scaling Theory - IEEE

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CONFERENCES scaling moved ahead to nanometer dimensions, things changed: Devices became more difficult to predict, and global performance degraded due to leakage and dispersion. One of the consequences of this deteriorating situation has been that increased parameter variability has led to a significant mismatch between simulation and actual measurement results, at all levels. While many of these effects have already been well known to analog designers, the surprise, now, is that they are more broadly important, even in digital design, where previously available noise margins have almost disappeared. Clearly, deep understanding and modeling of all underlying physical causes is urgently required to guide the right choices at all levels. Conceptually, such understanding will lead to acceptable levels of performance, manufacturability, and yield, at ever-decreasing feature sizes. Meanwhile, the increased parameter variability observed today, as one technology node invites the next, reveals the tight coupling of the four seemingly- independent dimensions of design, motivating the need to configure a new nano-cosmology, one in which global optimization results only from an intricate balance between the Process, Device, Circuit, and System aspects of design. In this new nano-cosmology, the emerging concept of Generalized Design-for-Manufacturability (GDfM) unifies current Design-for- Manufacturability (DfM), Manufacturing-for-Design (MfD), and Design-for-Yield (DfY), coupling all of the above-mentioned dimensions within a new space where their inter-dependence is revealed and exploited. Tightly coupled physical-electrical-mechanicalprocess modeling and simulation, will allow early detection of the impact of design choices at all levels. This creates a 4D knowledge continuum reminiscent of the ideas of General Relativity, ones extremely rich in consequences for the future of nanoelectronic design. More information about ISSCC 2007 may be found at: http://www.isscc.org/isscc/. Advances in Analogue Circuit Design Conference (AACD) Will Convene on 27-29 March 2007 16th Annual Workshop to Showcase European Expertise in Semiconductor Design Applications Jan Craninckx, Chair, SSCS-Benelux, cranincj@imec.be, Jan Sevenhans, SSCS Region 8 Representative, jan_sevenhans@amis.com, Jan Van der Spiegel, SSCS Chapters Chair, jan@seas.upenn.edu The 16th annual AACD workshop will be held on 27 – 29 March, 2007 in the Hotel Thermae Palace at the beautiful beach resort of Oostende, Belgium. SSCS is a technical cosponsor of this conference. The Thermae Palace, a unique seaside hotel in Art Deco style, is conveniently located within walking distance of the bustling Oostende city centre. The three-day workshop will feature 18 excellent speakers on the following topics: • Sensors, Actuators and Power Drivers for the Automotive and Industrial Environment (Tue 27 March) • Very High Frequency Front Ends (Wed 28 March) • Integrated PA’s from Wire line to RF (Thu 29 March) A panel discussion will be organized every evening on the topic of the day to ensure a lively interaction with the audience. The AACD technical program committee for 2007 consists of • Herman Casier, AMI Semiconductor Fellow, Belgium • Michiel Steyaert, Catholic University, Leuven • Arthur Van Roermund, Eindhoven University of Technology. Europe has expertise in a rich variety of semiconductor design applications: high-reliability and high-voltage automotive, medical for hearing aids and bio sensors, space radiation hard circuits and telecom mixed signal and multimedia, among others. Each year, a European company takes the initiative to support the AACD local and logistic organization to give the technical program committee leaders a free hand to invite the best international speakers for this three-day summary of advances in analogue circuit 78 IEEE SSCS NEWSLETTER Winter 2007
design. This year, the AACD local organisation is supported by the Communication High Voltage Product group of AMI Semiconductor in Belgium, represented by Jan Sevenhans PhD, IEEE fellow, and technically co-sponsored by IMEC, Leuven, Belgium in cooperation with the SSCS-Benelux chapter. Willy Sansen (KU Leuven), Jan Huijsing (TU Delft) and Rudy Van de Plassche (Broadcom) started the AACD annual workshop in 1992 with the goal of bringing together analog circuit design experts in Europe. The proceedings with full paper contributions have been published each year summarizing the state of the art. Over the past 15 years, the AACD workshop has covered timely topics such as biomedical circuits and sensors, telecom wireline copper and fiber optics, wireless public and LAN mixed signal systems on a chip, RF and baseband analogue radio circuits in bipolar and CMOS technologies, DSL drivers, A/D & D/A converters, low noise amplifiers, etc. It has taken place in Scheveningen, Leuven, Eindhoven, Villach, Lausanne, Como, Copenhagen, Nice, Munich, Noordwijk, Spa, Graz, Montreux, Limerick and Maastricht. It will be our pleasure to wel- CONFERENCES From left, Jan Van der Spiegel, SSCS Chapters Chair (University of Pennsylvania), Jan Craninckx, SSCS-Benelux Chair (IMEC, Belgium), and Jan Sevenhans, SSCS Region 8 Representative (AMI Semiconductor). From left, Dr. Van De Plassche, Dr. Sansen and Dr. Huijsing at the inaugural AACD conference in Scheveningen, The Netherlands, 1992. come a large group of silicon circuit and technology engineers and researchers involved in analogue and RF IC design in automotive, telecom and all industrial and other applications for this 16th AACD! More information may be found at www.aacd.ws/ and aacd2007@ amis.com Winter 2007 IEEE SSCS NEWSLETTER 79
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SSCS SSCS IEEE SOLID-STATE CIRCUITS
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Winter 2007 Volume 12, Number 1 Edi
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Analog IC Design at the University
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causes so-called random telegraph s
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costs associated with it can be sha
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A 30 Year Retrospective on Dennard
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Figure 5: Copper interconnects with
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improvements in process control, cy
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y circuit designers. One of the key
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Recollections on MOSFET Scaling By
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try settled on 5V supplies in the e
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products. Although the growth rate
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processors with increasing transist
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10. References 1. G.E. Moore, “Pr
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Fig. 2. Schematic of a CMOS device
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Page 33 and 34: It’s All About Scale Hans Stork,
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