The Impact of Dennard's Scaling Theory - IEEE

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However, a typical MOSFET in production in the
early 1970’s had a gate oxide of about 100 nm in
thickness, a channel length of about 5 μm, and a
power supply voltage of 5 V or larger. As explained
in a paragraph below, the performance of these highvoltage
MOSFET circuits was simply much too inferior
compared to the performance of silicon bipolar circuits.
Bipolar was the high-performance technology,
the backbone of computers and high-performance
electronics, while MOSFET was the low-cost technology
for applications where performance was not
required.
The benefit of applying the scaling theory to MOS-
FET technology, especially to CMOS technology,
seemed obvious and exciting. If we just follow the
rules and scale the CMOS devices by a factor of ten,
the resulting circuits will be ten times faster. For more
than two decades following the publication of the
MOSFET scaling theory, CMOS engineers focused
much of their efforts in scaling down the physical size
of CMOS transistors. However, instead of scaling
down the power supply voltage, they left it at 5 volts,
which was the standard for practically all integrated
circuits. There was simply little or no market for integrated-circuit
chips using non-standard voltages. Such
constant-voltage scaling of MOSFET quickly ran into
two major difficulties, namely the power density of a
CMOS circuit in switching increased very rapidly by a
factor of κ 2 to κ 3, and the fast increasing electric field
caused hot-electron and oxide reliability problems.
Power density was not much of a problem because
the integration level was still relatively low so that the
total chip power was readily manageable. However,
device engineers had to devote much effort to develop
practical techniques, such as LDD (Lightly Doped
Drain) [4], in order to bring the reliability issues under
control. Controlling hot-electron effects added significant
cost to the CMOS chips.
Scaling at constant voltage severely limited the performance
potential of CMOS as well, particularly for
driving long wires and driving signals off chip. To first
order, the performance for driving a capacitance load C
is CV/I, where V is the voltage swing and I is the current
delivered by the transistor. For bipolar circuits, V is
typically about 200-400 mV for driving on chip, and
about 800 mV for driving off chip. Thus, at 5 V, the voltage
swing of CMOS circuits was much too large for
high-performance applications. Besides, in the late
1970’s, bipolar engineers also developed a theory for
scaling bipolar circuits [5] which guided the rapid
development of faster and lower-power bipolar circuits.
For more than twenty years after the MOSFET theory
was published, CMOS remained a low-cost technology
limited to applications where performance was not an
important factor. When performance was needed,
scaled advanced bipolar technology was used.
The opportunity for scaled CMOS to break into
high-end applications came when the industry
worked together to established voltage standards
below 5 volt. Once it was recognized that CMOS at
less than 5 V could be accepted by the market, engineers
wanted to reduce CMOS voltage as fast as possible.
As an illustration of this “lower is better” mind
set at the time regarding CMOS voltage, Figure 1 is a
plot of three CMOS voltage roadmaps proposed in the
early and mid 1990’s. At the first semiconductor technology
roadmap workshop in 1992 [6], there was a
consensus that CMOS power supply voltage would
not be below 2 V until 2004. In 1995, it was proposed
that leading CMOS should have a power supply voltage
of 1.8 V in 1999. By the time the 1997 roadmap
[7] was prepared, it was proposed that the voltage in
1999 should be 1.5 V instead. For several years now,
advanced CMOS microprocessor chips use a power
supply voltage of 1 to 1.2 V.
Fig. 1. Proposed power supply voltage trends for CMOS.
(After references [6] and [7])
Reducing CMOS voltage makes the fabrication
process for scaled CMOS less complex and hence
lowers the cost. For one thing, process steps used to
implement LDD can be omitted. With the introduction
of scaleable technology elements such as shallowtrench
isolation and dual-poly gate (i.e., p+-polysilicon
gate for p-FET and n+-polysilicon gate for n-FET)
to the fabrication of reduced-voltage CMOS circuits,
as illustrated in Fig. 2, CMOS technology became
readily scaleable [8]. The same device schematic in
Fig. 2 was used to represent several generations of
CMOS technology, making the migration of devices
and circuits from one generation to the next relatively
simple to implement, and exhibited more predictable
results. For the decade that followed, there
was accelerated progress throughout the semiconductor
industry scaling such a CMOS device structure to
ever smaller dimensions, as evidenced by the accelerated
rate at which CMOS power supply voltage was
reduced.
With CMOS channel lengths scaled to around 100
nm and voltages reduced to around 1 volt, the performance
of digital CMOS became comparable to that
28 IEEE SSCS NEWSLETTER Winter 2007