The Impact of Dennard's Scaling Theory - IEEE

y circuit designers. One of the key parameters is
poly linewidth, since it has the dominant effect on
MOS transistor electrical performance. For 90nm
technologies, more than 50% of the variance in poly
line width comes from within-die (within field) variations.
The next component is die-to-die. The percentage
of systematic variations increases with
device scaling. For 90nm NMOS transistors, it reaches
40% of the overall Across Chip Variance (ACV).
Transistors behave differently based upon the
neighborhood layout pattern due to printability and
stress/strain effects. Moreover, printability and
Chemical Mechanical Polishing (CMP) cause significant
variations in interconnect parameters such as
resistance and capacitance.
2. New device architecture (UTB, dual gates) less
dependent on channel doping fluctuations:
Despite quite a few novel device architectures proposed
in recent years (FinFET, Ultra Thin Body
Transistor, Inverted T FET), the bulk CMOS device
architecture is used virtually exclusively at 45 nm.
It will most likely dominate the 32 nm nodes,
although SOI substrates are gaining more acceptance.
This leaves the device performance variations
very susceptible to random dopant fluctuations.
Performance boosters are additive and help, but
also create additional variability sources which
forces circuit designers to accept much higher variability
and as well as leakage currents.
3. Material improvements: high-k for gate dielectrics,
porous low-k for interconnects:
Several candidates for high-k materials have been
explored; but although Hf or Zr based oxides/silicates
provide attractive dielectric constant values
and are stable, they do require interfacial SiO 2 layers
between high-k layers and substrate/polysilicon.
The final stack is not as beneficial anymore.
Hence, high-k gate dielectrics are not employed in
the vast majority of 45 nm technologies and only in
combination with metal gates do they have a
chance at 32 nm.
4. Advanced process control (especially feed forward):
Given the increasing complexity and small process
windows, yield variability is a very significant problem.
Baseline process variability keeps on increasing
(tails of wafer yield distributions) and the present
metrology/inspection static sampling plans fail
at detecting excursions in-line. New approaches for
yield relevant SOC and APC are needed to take
advantage of the increased process observables
TECHNICAL ARTICLES
due to in-situ equipment sensor/FDC deployment.
5. Compact device models:
Below 100 nm, compact device models must
accommodate microscopic (i.e., “non-bulk”) physical
effects with minimal impact on overall computational
complexities. BSIM has filled this role for
many technology generations as the workhorse,
both for model characterization and node-to-node
technology predictions. It continues to have the
confidence of industry and seems likely to remain
in service (with the possible exception of RF) down
to about 45 nm.
More recent MOS models are formulated as functions
of surface potential, rather than threshold
voltage, in the channel and s/d edges. Surface
potential is directly linked to intrinsic channel
charge dynamics and enables addition of important
physical effects with an economy of model complexity.
The formulation admits an expression for
transistor drive current that is continuous from
accumulation to saturation, thereby avoiding the
necessity of matching multiple regions.
Compact models at 65 nm have high priority needs
for improvement:
(a) scalability of sub-threshold currents and output
resistance from short-to-long channel lengths,
due largely to lateral doping non-uniformities
(b) dependence of noise on voltage and geometry;
i.e., considering 1/f noise dependence on random
noise trap occurrences
(c) capabilities for handling geometrical statistical
fluctuations which affect noise, threshold voltage
and drive current.
The above problems become more severe at 45 nm,
along with the following additional priorities:
(1) gate current scaling and dependences on novel
(e.g., multi-layer) gate stacks,
(2) carrier mobility in the channel due to layoutinduced
stress/strain,
(3) statistical variations stemming from random
dopant placements,
(4) ballistic transport of carriers in intrinsic channel
and,
(5) quantum mechanical effects due to confinement
in thin films.
Summary
Scaling theory has been the organizing principle of the
progress of the semiconductor industry throughout
three decades. It has created a framework for continued
improvement in density and cost performance
and facilitated the desegregation of the entire industry
Winter 2007 IEEE SSCS NEWSLETTER 17