The Impact of Dennard's Scaling Theory - IEEE

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Message from the President In 2007, look for an unadvertised bonus with your SSCS membership: A free subscription to the brand new quarterly Nanotechnology Magazine. We believe that circuit experts need to be in touch with this rapidly progressing technology. Some day it will be a fruitful area for circuits development, and opportunities to contribute will arise. The minimal subscription cost to the Society for the launch year of the new magazine prompted the AdCom to join the Nanotechnology Council. We hope the Council’s magazine effort will be of comparable interest to its Transactions on Nanotechnology, which is just beginning its sixth year and has among the highest rates of citation as measured by the Thompson ISI. I would like to receive feedback from you on how useful a tool the new magazine is. Look for the first issue in the spring of 2007. 2007 is the Society’s 10th anniversary, having evolved from the Solid-State Circuits Council that originated in 1970. We’ve updated the SSCS logo for this year to draw attention to our progress. Since 1997, the Journal of Solid-State Circuits has increased coverage of technical articles by 40%, and the SSCS Newsletter by 2 1/2 times. The JSSC continues to be the most read in IEEE Xplore and the most cited in patents. Your SSCS membership provides online access not only to the Journal but also to the digests of our five major solidstate circuits conferences and most of their historic record. Local chapters have grown from 2 to 59, with Corrections In the article entitled “Overview of CMOS Technology Development in the MIRAI Project,” by Toshiaki Masuhara and Masataka Hirose in the September 2006 issue, the last sentence in the Section entitled “New Circuits and System Technology - Post-fabrication Adaptive Adjustment” contains an incorrect expression, which is corrected as in the underlined expression in the following sentence: “As shown in Fig. 3, the developed tool successfully extracted the 34 model parameters in 23 hours with a PC and resulted in a mean RMS error of 1.83% for benchmark MOSFETs.” In the Section, “New Gate Stack Technology with High-k Materials”, the caption for Figure 4 should read: Fig. 4 Gate leakage current in MIRAI HfAlON formed by Layer-by- Layer Deposition and Annealing (LL-D&A) 4 ). (a) Comparison of gate leakage current in MOSFETs with HfAlON gate insulator and HfSiON 5 ). (b) Cross sectional TEM micrograph of HfAlON/SiO 2 /Si gate stack formed by Layer-by-Layer Deposition and Annealing. The following corrections pertain to the reprint of “Lithography and the Future of Moore’s Law” (Moore, 1995) in the September 2006 issue: I have reproduced photomicrographs of the first planar transistor the recent addition of Tainan (Taiwan) and South Brazil. Celebrate our anniversary by browsing your technical articles online. I’ve been active in the last quarter attending many of the conferences that SSCS cosponsors to sample their quality, focus, and differences, as well as to increase the Society’s visibility and support for these important gatherings of technical experts. ESSCIRC in Montreux, Switzerland last fall was fully overlapped with the ESS- DERC device conference. One was able to move freely between the co-located meetings. The wide variety of plenary topics covered by the two meetings was of particular interest. Welcoming the Asian-Solid-State Circuits Conference in Hangzhou, China two months later, I was able to talk with circuit experts from around the world, and by the time this issue reaches you, I will have celebrated the opening of the 20th International Conference on VLSI Design in Bangalore. Thanks to all of our members who voted in our fall election. Welcome to our new additions to AdCom, Kevin Kornegay from Georgia Tech and Harry Lee from MIT. And welcome back to returning AdCom members John Corcoran from Agilent Laboratories, Tom Lee from Stanford, and Jan Van der Spiegel from the University of Pennsylvania. The Society is beginning a review of its priorities for 2007 and beyond. As Society members, please make your interests known to your AdCom representatives. Start a conversation and help the Society point to the future that you feel is coming. Richard C. Jaeger and the first commercially-available integrated circuit in Figs 3 & 4. I am particularly fond of the transistor, since it is one of the very few products that I designed myself that actually went into production. Fig. 3. Photomicrograph of the first commercial planar transistor. continued on page 10 4 IEEE SSCS NEWSLETTER Winter 2007
Analog IC Design at the University of Twente Bram Nauta, IC Design Group, University of Twente, Enschede, The Netherlands, b.nauta@utwente.nl Introduction This article describes some recent research results from the IC Design group of the University of Twente, located in Enschede, The Netherlands. Our research focuses on analog CMOS circuit design with emphasis on high frequency and broadband circuits. With the trend of system integration in mind, we try to develop new circuit techniques that enable the next steps in system integration in nanometer CMOS technology. Our research funding comes from industry, as well as from governmental organizations. We aim to find fundamental solutions for practical problems of integrated circuits realized in industrial Silicon technologies. CMOS IC technology is dictated by optimal cost and performance of digital circuits and is certainly not optimized for nice analog behavior. As analog designers, we do not have the illusion of being able to change CMOS technology, so we have to “live with it” and solve the problems by design. In this article several examples will be shown where problematic analog behavior, such as noise and distortion, can be tackled with new circuit design techniques. These circuit techniques are developed in such a way that they do benefit from modern technology and thus enable further integration. This way we can improve various analog building blocks for wireless, wire-line and optical communication. Below some examples are given. Thermal Noise Cancelling Noise is an important issue; in communication circuits the sensitivity of the receiver is limited by the noise level of the circuits. Especially, the noise of the first amplifier in the receiving chain is of high importance, since after that amplifier the signal is stronger and the allowable noise levels are higher. For narrowband receivers the added noise of the amplifier can be reduced relatively easily. This is done by using resonant structures, built with - for example - integrated spiral inductors and capacitors which provide voltage gain of the narrowband signals and therefore needing less gain from “noisy” transistors. For wideband systems, e.g. for TV tuners, UWB (Ultra Wide Band) communication and future software defined radio, several octaves of bandwidth are needed and simple resonant structures cannot be used. For these applications, low noise gain stages using noisy transistors have to be used, which is quite a challenge. Apart from the gain and noise demands, additional demands, such as input impedance matching and good linearity, need to be satisfied. RESEARCH HIGHLIGHTS Figure 1a shows a wide band first amplifier stage, denoted as a common-source feedback amplifier. Fig 1a: common source LNA with impedance matching, the signals at nodes X and Y have opposite sign. Fig 1b: The noise of M1 generates in-phase noise voltages at nodes X and Y. The input impedance is 1/g m of M1, and must be equal to the source impedance Rs, usually 50 Ohms. With this in mind the gm of M1 is fixed by design resulting in poor noise behavior of the amplifier: The "noise figure" is always larger than 3dB. In order to reduce the noise one would like to increase the g m of M1 (preferably g m>>1/Rs for minimal noise figure) but then the input impedance does not match anymore. Conventionally, additional feedback techniques are used to break this paradox, but at the cost of stability and bandwidth issues. PhD Student Federico Bruccoleri realized, however, that generated noise can be cancelled by proper circuit design. If we take a look at Figure 1b, we can see how the noise current of M1 flows in the circuit; this is indicated by the red arrow. The noise current due to M1 flows in a loop, through Rs. This noise current generates a noise voltage at nodes X and Y which are of different magnitude but of the same phase. The signals nodes X and Y are in anti-phase due to the inverting nature of this amplifier. So somehow it should be possible to separate the signal from the noise! By adding an additional amplifier “A,” as shown in Figure 2, we can construct an output signal in such a way the wanted signals at nodes X and Y are added and that the noise at nodes X and Y are cancelled [1]. This way we can cancel the noise of M1, which holds for both thermal and 1/f noise. Of course amplifier “A” will now add additional noise, but this needs not to be a problem. The reason for this is that in contrast to M1, we can choose the gm of the input stage of amplifier “A” relatively large, and thus make it low- Winter 2007 IEEE SSCS NEWSLETTER 5
Page 1 and 2: SSCS SSCS IEEE SOLID-STATE CIRCUITS
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Page 7 and 8: causes so-called random telegraph s
Page 9 and 10: costs associated with it can be sha
Page 11 and 12: A 30 Year Retrospective on Dennard
Page 13 and 14: Figure 5: Copper interconnects with
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Page 17 and 18: y circuit designers. One of the key
Page 19 and 20: Recollections on MOSFET Scaling By
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Page 33 and 34: It’s All About Scale Hans Stork,
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Page 37 and 38: The one-dimensional threshold model
Page 39 and 40: Fig. 1. Illustration of device scal
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James Meindl, friend and pioneer of
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60 faculty members from MIT, Stanfo
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cult to get the idea of mixed signa
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about the time he left OSU for Ariz
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16 New Speakers Will Diversify the
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to control VTH through substrate bi
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cal Engineering. His current resear
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MOSFETs and clarified the importanc
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SSCS Awards $35,000 in Chapter Subs
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CHAPTERS V. Oklobdzija Offers IEEE
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CHAPTERS Herman Pang (far left) and
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(2) A 0.98 to 6.6 GHz Tunable Wideb
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Semiconductor), Bram Nauta (Univers
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design. This year, the AACD local o
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the IEEE. These activities range fr
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Freedom TO INNOVATE IEEE Member Dig
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