The Impact of Dennard's Scaling Theory - IEEE

TECHNICAL ARTICLES
from metal gate electrodes by eliminating the depletion
layer on the top side of the dielectric. Any
mobility degradation because of additional scattering
will be overcome by the significant mobility
enhancements due to strain. In fact, the successful
application of strain is a superb example of unanticipated
improvements that work precisely because
of the new small scale of the devices. Many of the
effects below 100nm introduce problematic behaviors:
tunneling contributes to leakage in thin
dielectrics and high field junction profiles; line edge
roughness in resists patterns results in excessive
short channel effects; and grain–boundary and sidewall
scattering increase the resistivity of copper
wires with very small cross-sections. Low resistance
is critical to high efficiency use of the device properties.
Contact and via resistance are therefore
becoming a bigger concern going forward as their
properties scale non-linearly in the wrong direction.
And, as many now know, the capacitance of the
interconnect is approaching its physical limits as
well. The low dielectric constant materials that
reduce the k-value from 4 for silicon dioxide, to
around 2.5 for heavily Carbon mixed compounds,
are mechanically weak and can interfere with packaging
robustness, as well as cause electrically lower
breakdown voltages.
All these process and materials changes have
allowed density scaling to continue at its historical
pace of 2x every generation. The price has not only
been more complexity, but also the introduction of
several design tradeoffs. Design innovations now
need to limit static and dynamic power dissipation,
tolerate escalating parameter variations, maximize
increasingly restricted layout options, and incorporate
analog and RF functions at the low voltages compatible
with extremely small dimensions.
Scaling the Resources
Immersion lithography allows for effectively shorter
wavelength and a higher NA lens design to improve
the lithographic patterning pitch. A manufacturable
implementation requires cost effective throughput,
defect density, and resist solution. The large increase
in capital equipment cost consumes the largest fraction
of the process cost budget. As is the case for
every process tool, to maintain cost effectiveness,
high throughput/automation is required to offset the
initial capital outlays. But now the high volume
capability of each tool requires the fabs to be ever
larger to avoid one-of-a-kind tool challenges. In
addition, chips now may include over 10 layers of
interconnect. While the process is repeatable, the
interconnect fraction of a fab is easily half the fab
size because of the multitude of tools. The explosion
in process steps, represented typically by the num-
ber of mask layers has also increased rapidly. The
size and cost of fabs has thus grown exponentially,
each supplying an ever larger fraction of the market,
and each generation requiring a larger investment
and higher market risk.
Resource demands have also rapidly grown on the
product side. Thanks to the ability to yield hundreds
of millions of transistors on a single die, design teams
for chips are now equivalent to those that were
required to build large computers. Product designs
need to comprehend everything from knowing the
strengths and limitations of the process, to defining
and building the software infrastructure that support
such sophisticated systems-on-a-chip.
Scaling the Applications
Absolute interconnect performance has become a
dominant speed limit and, consequently, variations in
line-width and thickness add increasingly to the
design margin. While many effects are systematic, the
complexity of interconnect prevents a brute force
computational solution. This has become typical of
the technical problems to be solved at the design and
application level. Conceptually, the problem of optimizing
interconnects to minimize delay and power is
governed by simple physics. However, the sheer size
of a problem like this, or that of RET or for that matter,
fab operations, is overwhelming. Not just for the
design teams, but frequently for their compute
resources as well. And finally, the challenge is not
overcome by solving a steady state or exact condition.
Parameters are not perfectly controlled, and it is
becomingly increasingly clear that comprehending
variations is where the next breakthrough may be
needed. Nature gives us examples of how it has figured
out that designing with imperfect and infinitely
variable components can be successful. Although
human communication may be effective while being
imperfect, other communication or computation tasks
cannot tolerate any practical errors.
For example, encouraging progress by the EDA
tool suppliers is trailing the needs for leading product
designs. Integrating analog and RF functions in
advanced CMOS requires an architectural approach to
maximize the features of density and speed, rather
than the precision of analog components.
Summary
Over the past 40 years the world has benefited from
exponential growth in the application of semiconductors.
Thanks to scaling transistor dimensions into the
nanometer regime and scaling the manufacturing
capabilities to produce billions of individual chips, the
industry has achieved economies of scale that allow
what was once mainframe capability to be affordable
to everyone in the world in something as small as a
34 IEEE SSCS NEWSLETTER Winter 2007