The Impact of Dennard's Scaling Theory - IEEE

Fig. 2. Schematic of a CMOS device structure that was
scaleable to deep sub-micron dimensions. (After Davari, [8])
of digital bipolar. The era of bipolar for high-performance
digital circuits came to an end when IBM
decided to replace bipolar by CMOS as the technology
for mainframe computers. At first, the CMOS mainframe
processors was not really as fast as the bipolar
versions, but the highly scaleable properties of CMOS
allowed CMOS processors to catch up in just a few
years, as shown in Fig. 3 [9]. Since then, CMOS has
become unquestionably the technology for all digital
applications.
Fig. 3. IBM S/390 mainframe uniprocessor performance.
(After Rao et al., [9])
Every technology has its limits, and CMOS is no
exception. The fact that the CMOS device structure
depicted in Fig. 2 is highly scaleable was both good
news and bad news. The good news was that it
became relatively straight forward to establish an
industry-wide technology roadmap, and every leading
semiconductor company wanted and was able to beat
the roadmap targets. Again, this is evidenced by the
increasingly aggressive rate of CMOS power supply
voltage reduction illustrated in Fig. 1. System developers
and consumers certainly benefited tremendously
from the faster-than-projected rate of CMOS scaling.
The bad news was that the industry also reached the
limits of CMOS scaling at rate faster than anticipated.
Two of the limits of CMOS scaling were reached in the
TECHNICAL ARTICLES
early 2000’s. These limits are the high tunneling current
through the thin gate insulator and the high device off
current. That we reached these scaling limits so soon
should come as no surprise. In the case of gate insulator
thickness, it was shown that scaling CMOS to the regime
where gate tunneling current is appreciable has little
impact on the device characteristics [10]. Today, leadingedge
CMOS microprocessor chips employ gate oxide layers
as thin as 1 nm, which is pretty much the limit set by
acceptable gate tunneling current. The limit due to high
device off current has been looming there since the very
beginning, as shown in Eq. (1). In Eq. (1), the factor
[Vg − Vt − Vd /2]/κ scales only if the threshold voltage
V t is scaled. If V t is not scaled, this factor is smaller than
expected from scaling and the resultant device speed is
less than expected from scaling. As the CMOS voltage
was scaled below about 2 V, device designers had to
reduce V t in order to achieve the intended device performance
targets. Reducing V t has the effect of increasing
the device off current, as illustrated schematically in Fig.
4. Reducing V t repeatedly for several generations has lead
to a dramatic increase of CMOS device off current.
Today, CMOS circuits no longer have negligible standby
power dissipation. Instead, the performance of leadingedge
CMOS logic chips is limited by a combination of
device off current and gate tunneling current.
Fig. 4. Schematic showing the increase of device off current
when V t is reduced, where V t2 < V t1 .
Without the ability to reduce gate insulator thickness
and device threshold voltage any further, CMOS device
designers find it difficult to increase device speed by the
usual means of scaling device channel length. Today,
device engineers focus primarily on technology innovations
for continued device performance improvement
from one generation to the next. The most notable innovations
that have been successfully developed and put
into volume manufacturing to date include using siliconon-insulator
(SOI) as the wafer substrate [11], using
embedded SiGe in the source/drain region of p-channel
FET’s to improve hole mobility [12], and using highlystressed
dielectric films on top of n-channel FET’s to
improve electron mobility [13]. Each of these innovations
offers incremental but appreciable improvements to the
Winter 2007 IEEE SSCS NEWSLETTER 29