The Impact of Dennard's Scaling Theory - IEEE

to control VTH through substrate
bias, and applied it to a DCT core
processor and a gate-array in 1995.
He also developed a Variable Supply-voltage
scheme using an
embedded DC-DC converter, and
employed it to a microprocessor
core and an MPEG-4 chip for the
first time in the world in 1997. In
2000, he moved to Keio University,
Yokohama, Japan, where he has
been a professor since 2002. He
has been a Visiting Professor at
Hiroshima University, Japan, and
the University of California, Berkeley.
His research interests include
low-power, high-speed CMOS
design for wireless and wireline
communications, human computer
interactions, and ubiquitous electronics.
He has published more
than 200 technical publications,
including 50 invited papers, and 18
books/chapters, and has filed
more than 100 patents.
Dr. Kuroda served as the General
Chairman for the Symposium on
VLSI Circuits, the Vice Chairman
for ASP-DAC, sub-committee
chairs for A-SSCC, ICCAD, and
SSDM, and program committee
members for the Symposium on
VLSI Circuits, CICC, DAC, ASP-
DAC, ISLPED, SSDM, ISQED, and
other international conferences.
He is a recipient of the 2005 IEEE
System LSI Award, the 2005 P&I
Patent of the Year Award, and the
2006 LSI IP Design Award. He is an
IEEE Fellow and an IEEE SSCS Distinguished
Lecturer.
John R. Long received
the M.Eng.
and Ph.D. degrees
in Electronics from
Carleton University,
Canada in 1992 and
1996, respectively.
He worked for 10 years at Bell-
Northern Research, Ottawa (now
Nortel Networks) designing ASICs
for Gbit/s fibre systems, and for 5
years as a faculty member at the
University of Toronto. He joined
the faculty at the TU Delft in Janu-
ary 2002, where his current
research interests include: lowpower
transceiver circuitry for
highly-integrated radios and electronics
design for high-speed data
communications. Professor Long
currently serves on the program
committees of the ISSCC, ESSCIRC,
IEEE-BCTM and GAAS 2004, and is
a past Associate Editor of the IEEE
Journal of Solid-State Circuits.
Toshiaki Masuhara
(S768-M’69-SM’90-
Fellow’94), Association
of Super-
Advanced Electronics
Technologies
(ASET), was born on
Mar. 5, 1945 in Osaka, Japan. He
obtained B.S., M.S. and Ph.D.
degrees in Electrical Engineering
from Kyoto University, Kyoto, Japan
in 1967, 1969 and in 1977, respectively.
From 1969 to 1974, he was a
member of the technical staff, 3rd
and 7th Department at Hitachi Central
Research Laboratory(CRL),
Kokubunji, Tokyo, Japan, where he
worked on depletion-load NMOS
integrated circuits and on modeling
of sub-threshold characteristics of
MOS transistors. From 1974 to 1975,
he was a special student, Department
of Electrical Engineering and
Computer Science, University of
California, Berkeley where he
worked on double-diffused MOS
transistors and a new CMOS
process. In 1975, he returned to
Hitachi CRL and worked on new
high speed CMOS SRAM. In 1987,
he became department manager,
7th Dept., Hitachi CRL, developing
memories, microprocessors, digital
signal processors and high frequency
silicon devices. He then became
the manager of the 1st Dept. in
1990, performing research on high
speed GaAs and bipolar ICs and
materials. From 1991 to 1993, he
was in Telecommunications Division,
Hitachi, where he was responsible
for the design of telecom
ICs.He became General Manager,
Technology Development Opera-
PEOPLE
tion (Center) in 1993, General Manager,
Semiconductor Manufacturing
Technology Center, Semiconductor
& IC Div. in 1997, and then became
Senior Chief Engineer, Semiconductor
Group, Hitachi. In 2001, he
assumed his current position, Executive
Director, MIRAI Project, Association
of Super-Advanced Electronics
Technologies (ASET).He is a
member of IEEE and IEICE, Japan.
He became a fellow of IEEE in 1994
with the citation, ”For contribution
in the invention and the development
of NMOS circuits and highspeed
CMOS memories”. He was
the program co-chair and the chair
in 1992-, 1993-, and general co-chair
and chair in 1996- and 1997-VLSI
Circuit Symposium. He was an
elected member of the Administrative
Committee, SSCS from 1998 to
2000.He received IEEE Solid-State
Circuit Technical Field Award on his
contribution to NMOS depletionload
circuits and the development
of high speed CMOS memories in
1990 and the IEEE third Millennium
Medal in 2000. He has received a
Significant Invention Award, Japan
in 1994, four Significant Invention
Awards, Tokyo, Japan in 1984, 1985,
1988 and 1992, Significant Invention
Awards, Yamanashi, Japan in 1995
and Gumma, Japan in 1996.
Akira Matsuzawa
received B.S., M.S.,
and ph. D. degrees in
electronics engineering
from Tohoku
University, Sendai,
Japan, in 1976, 1978,
and 1997 respectively. In 1978, he
joined Matsushita Electric Industrial
Co., Ltd. Since then, he has been
working on research and development
of analog and Mixed Signal LSI
technologies; ultra-high speed
ADCs, RF CMOS circuits, and digital
read-channel technologies for DVD
systems. From 1997 to 2003, he was
a general manager in advanced LSI
technology development center. On
April 2003, he joined Tokyo Institute
of Technology and he is a professor
Winter 2007 IEEE SSCS NEWSLETTER 63