The Impact of Dennard's Scaling Theory - IEEE

The largest question in the early to mid 70’s was
how far silicon could go in competition against
newly emerging materials and devices such as
magnetic bubble memory, Gunn effect functional
devices, integrated injection logic, GaAs MESFET integrated
circuits, and Josephson junction logic.
The typical roadmap of major semiconductor
manufacturing companies in those days was such
that (1)Silicon based integrated circuits would lose
position by the mid 80’s except for silicon on sapphire,
SOS, based ones, (2)GaAs integrated circuits
would become the dominant design for high speed
and /or low power applications, (3) Optical lithography
would surrender its position against either
electron beam lithography or soft X-ray lithography,
(4) Geometry shrink, however, may proceed
despite challenges around. In other words, no one
was even close to predicting what we are seeing
today. In fact, many central research organizations
in industry decided that silicon would not be a right
subject any more for advanced research, and either
shut down silicon research activities or transferred
the division to their operation divisions.
In the middle of the 70’s, Japan launched a large
national project, called the “VLSI project” which was
instigated by the announcements made by Bell Laboratories
for electron beam direct writing lithography,
and by IBM demonstrating 8kbit dynamic random
access memory at 1um minimum geometry,
both of which were supposed to provide solutions
for future computing systems in the mid 80’s and
beyond. The project consisted of Fujitsu, Hitachi,
Mitsubishi, NEC and Toshiba, and had a centralized
research center for basic research to which all member
companies sent researchers, and also two branch
laboratories for Fujitsu-Hitachi-Mitsubishi group and
NEC-Toshiba group focused on more development
oriented work. Two government laboratories, Electrotechnical
Laboratory and NTT Laboratories were
also involved.
Moore’s Law was already becoming popular, but
when it came to any methodical approach to make
it happen rather than a religious belief, there was not
much idea which was viewed credible enough.
Japan’s VLSI project had both logic and memory as
the targeted areas with MOSFETs, bipolar such as
ECL/CML, and compound semiconductor devices.
The tool side was even broader, covering from optical,
electron beam and X-ray lithography, plasma
TECHNICAL ARTICLES
Impact Of Scaling and the Scaling Development
Environment
Yoshio Nishi, Department of Electrical Engineering Center for Integrated Systems,
Stanford University, yoshio.nishi@stanford.edu
processes and a variety of thermal processes. This
almost implied that we needed to look around for
360 degree instead of any particular focus. Also, it
was the time when layout design was viewed as
such a serious bottle neck that almost 90% of the
world population might need to become layout
designers and technicians by the end of the 80’s.
Fortunately, many IEEE technical conferences, such
as IEDM and ISSCC were quite interesting in terms
of a large variety of research results presented, but
when it came to the future of silicon integrated circuits,
general perception was to seriously stagnant at
around 1um geometry.
Dr. Robert Dennard’s paper in 1974(1) appeared in
the IEEE Journal of Solid State-Circuits. As the first
proposal for the scaling principle, it looked, at first
glance, rather simple and did not attract much attention,
at least I remember from a little corner of Toshiba
Research and Development Center where I was in
charge of SOS microprocessor technology and also
involved in Japan’s VLSI project looking into short
channel MOSFET technology research. However, it
did not last long before more people started understanding
what it possibly would imply to the world
of MOS integrated circuits. However, it needed to
wait for CMOS taking the “dominant” design position
in the mainstream of integrated circuits before the
scaling theory became the physics based guiding
principle for Moore’s Law to continue. Without scaling
theory, I doubt that Moore’s Law could have survived
for more than three decades. It was the first
attempt to couple geometry shrink with other important
factors such as power-delay products, on-chip
interconnect performance as well as integration density.
The magic number alpha of “1.4” or 0.7x shrink
over all device parameters, as shown below became
a general guideline from one technology node to the
next technology node since then.
dimensions tox, L, W 1/α
doping α
voltage 1/α
integration density α 2
delay 1/α 2
power dissipation/Tr 1/α 2
It is indeed difficult to see any other such example
in which one set of rather simple principles can
survive for such a long time. I would, however, say
Winter 2007 IEEE SSCS NEWSLETTER 31