The Impact of Dennard's Scaling Theory - IEEE

TECHNICAL ARTICLES
Five areas of critical challenges that could decrease
the rate or even stop the progress of scaling of Semiconductor
technology were identified:
• Patterning material and processes for device
structures below 0.25μm
• Electrical interconnections, both on and off chip
• Electrical test, time cost and capability
• Design, modeling, simulation capability for all
elements of IC technology and products
• Software capability, availability and quality for all
aspects of IC technology and production.
As we look back at the last 15 years now at the end
of 2006, this roadmap has truly focused the investment
and made most of the predictions come true.
Emergence of Foundry Manufacturing
Companies
As the process technology scaling became more systematic
the disaggregating of IC manufacturing
became a reality. Since the establishment of TSMC in
1987 to satisfy customers’ needs under the disintegration
trend, the pure play foundry industry has grown
to a multi-billion business. In turn, the pure play
foundry business model has further accelerated the
disintegration trend in the semiconductor industry.
In the past decade, leading foundry companies have
caught up with the leading IDMs (Integrated Device
Manufacturers) in process technology prowess. The
technological challenges of foundry companies in the
next decade will be even more challenging than those
of leading IDMs because of the need to emphasize
more on process versatility, cost effectiveness and easy
adoption by diversified customers.
The specific technology development challenges of
a successful foundry company in the next decade
include: (1) aggressive scaling of transistors, interconnect,
and design rules for both performance and density;
(2) embedded technologies for SOC solutions; (3)
cost effective and manufacturability process technology;
(4) a versatile technology portfolio; and (5) easy
integration among customers, design service/IP
providers and the foundries.
In the next decade, the foundry paradigm is
expected to play an even more important role as
foundry companies continue to build their core competencies,
including leading-edge process technologies,
advanced and flexible manufacturing capabilities,
and customer-oriented services systems. The
strong entrenchment of the foundry industry will further
move the semiconductor industry in the direction
of complete disintegration.
Scaling continues to be the Treadmill of the
Semiconductor Industry
Looking back at the last few years since the first SIA
workshop, the ability to marshal and focus the invest-
ments of the entire industry on the key technology
issues has indeed been an enabler for scaling down
to 90nm. The top three among these are:
1. Sub-wavelength optical lithography (including
OPC/Resolution Enhancement Techniques):
Advances in scanners and resist technology
enabled printing features less than one-half of the
light wavelengths. Chemically amplified resists,
light polarization, phase shifting techniques (alternating
apertures and attenuated), as well as comprehensive
Model Based Optical Proximity Corrections
of critical layer layouts, are the key enablers.
2. Extending bulk CMOS by several performance
boosters - stress/strain, ultra shallow junctions, and
ox nitrides:
Conventional bulk CMOS device architectures have
been extended to 90 nm and below technology
nodes by employing several performance boosters
such as:
- bi-directional stress/strain layers to enhance
carrier mobility for both electrons and
holes,
- ultra-shallow junctions obtained by very
low energy implants and flash/laser
anneal
- very thin (1.2 nm) gate ox nitride layers that
provide uniform layers, good interface to
both substrate and polysilicon gate and prevent
Boron penetration.
3. Multilevel Cu interconnect including CMP:
Up to 12 layer of Cu interconnect layers have been
achieved thanks to Double Damascene Cu deposition/patterning
technology and improvement in chemical
mechanical polishing. Dishing/erosion effects
have been reduced by applying smart dummy fill and
additional manufacturability layout design rules to
eliminate wide lines/small spacing patterns and drastic
density variations within each interconnect layer.
As we look forward to the continuation of these 30
years of scaling progress, there are similar challenges
to overcome to scale to 45nm and below:
1. Device/process variability 9:
Process variability sources can be categorized based
on the spatial hierarchy: lot-to-lot, wafer-to-wafer,
within-wafer or within-die, or root causes (random
or systematic). These sources create a complicated
distribution of parameters that must be addressed
16 IEEE SSCS NEWSLETTER Winter 2007