The Impact of Dennard's Scaling Theory - IEEE

TECHNICAL ARTICLES
Such technology scaling was achieved typically in
the following manner:
a. Drive new photo lithography equipment and
processes that allowed printing and patterning of
dimensions 30% smaller than in the previous
generation.
b. Make improvements to other parts of the
process, e.g., gate oxidation, ion implantation,
diffusion, etching, interconnect metallurgy etc.
c. Engineer and optimize the transistor device
structure and various aspects of the process to
meet performance and cost goals, and be manufacturable
and reliable.
d. Execute a “Linear Shrink” of an existing product
reducing the die size by a scaling factor such
as 0.7. Due to various intricacies of the process,
the design rules and device characteristics at
shrinking geometries, such scaling became
increasingly difficult. In the mid-1980’s such an
approach, which was referred to by some people
as a “dumb shrink” became known as an
“intelligent laborious shrink” at some companies.
e. A new set of design rules - both physical and
electrical - were usually used to design new
products that took full advantage of the new
technology capability. While the shrink approach
was able to get an initial product out in the new
technology node, the “Re-Design” approach was
necessary to maximize performance and minimize
cost of products in the new node.
f. In addition, the new technology usually had some
new features aimed at increasing the packing efficiency,
design productivity and device performance.
Some examples are: increasing the number
of metal interconnect layers, self-aligned polysilicon
gate structure, oxide and trench isolation,
standard cells, EDA tools and re-usable IP blocks.
We will now discuss migration of designs from one
node to the next using either the “Linear Shrink” or
the “Re-Design” approach. To illustrate the “Linear
Shrink”, consider Figure 4(a), which depicts a square
die with dimension y and having N transistors, in
technology node T1. A simple shrink of the die into
technology node T2 would reduce the die size by the
scale factor k, where 0