The Impact of Dennard's Scaling Theory - IEEE

TECHNICAL ARTICLES
Ion Implanted MOSFET’s With Very Short Channel
Lengths
R. H. Dennard, F. H. Gaensslen, H. N. Yu, V. L. Rideout, E. Bassous , and A. LeBlanc
IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.
Copyright 1973 IEEE. Reprinted with permission. Technical Digest, IEEE International Electron Devices Meeting, 1973, pp. 152-155.
It has been shown previously that MOSFET switching
devices can be scaled down to have one micron spacing
between source and drain. In order to achieve
electrical characteristics suitable for dynamic memory and
other digital applications, such miniaturized devices must
have reduced gate insulator thickness and junction depth,
reduced operating voltages, and increased substrate doping
(1). The previously described one micron device
structure is shown in Fig.1(a). With uniform substrate
doping, a 200°A gate insulator is required to achieve the
desired control of the gate threshold voltage over the
operating range of the source and drain voltages.
Figure 1: MOS device designs for micron source-drain
spacing. (a) Unimplanted design (b)Design with ion
implantation.
The present paper addresses improvements in the
design of micron devices which can be obtained by
using ion implantation. The new n-channel design,
which is shown in Fig. 1(b), uses a lighter doped substrate
with a relatively heavy doped p-type region at the
surface between the source and drain. This implanted ptype
region gives the desired threshold magnitude, and
also controls the extent of the source and drain depletion
regions beneath the gate. With the gate turned off,
these depletion regions must be kept separated so that
the surface potential in the channel region is indeed
controlled by the gate. Merging of the depletion layers
in the lighter doped substrate is prevented by using shallow
implanted source and drain junctions of depth comparable
to the p-type implanted region, and also by
choice of a moderate substrate doping level.
Figure 2(a) Vertical substrate doping profile, and (b) the
resulting threshold versus source - substrate bias characteristic
compared with alternate approaches. Experimental
confirmation is shown by large dots.
The vertical-doping profile of the implanted region
beneath the gate is shown in Fig. 2(a). Intuitively, it was felt
that a step function profile is preferable for the one micron
implanted device, and such a profile has been used for
design purposes. In practice a single energy implant
through the gate oxide with thermal treatment used in the
subsequent processing gives a reasonably good approximation
to the step function. Fig. 2(b) shows the gate threshold
voltage (relative to the source) required to turn on the
device as a function of the source - substrate potential using
the one-dimensional model described in another conference
paper (2). The implantation profile was chosen to be
deep enough to prevent depletion layer punch through,
and shallow enough to give the desired threshold voltage
control with a 350°A gate insulator thickness. Throughout
the operating bias range (Vs-sub > 1), the gate field for the
threshold condition depletes the heavier doped implanted
region, and this depletion extends well into the lighter
doped substrate. This gives a threshold voltage relatively
independent of source-substrate bias compared to a uniformly
doped substrate with the same 350°A oxide thickness.
(See Fig. 2(b)). Compared to a non-implanted design
with a 200°A gate insulator, the new design has the same
slope in the threshold versus source bias characteristic, but
the overall threshold level is higher, which is desirable to
provide adequate design margins for circuit applications.
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