tesi R. Miscioscia.pdf - EleA@UniSA

Gate-leakages 91
It has to be considered that the increase of gate current is
provoked by a complete overlap between contacts and gate and a
relatively small gate-source and gate-drain separation (in the figure 5
it has to be 1.000µm (insulator) + 65nm (pentacene) = 1.065 µm)
figure 6: Output characteristics of PI device before annealing (dotted: experimental; line: model
fitting simulations of eq. 1).
The fitting results (figure 6 and eq. 1 with the common meaning of
symbols) reveal that the gate leakage current is related to the gatedrain
voltage, if drain was biased (VDS ≠ 0). After the annealing
process, the output characteristics change (see figure 7), restoring the
zero-crossing at VDS = 0 V. Consequently, we can state that gate
leakage-current reduces and the device approaches a quasi-ideal FET
operation (i.e.: α = 0).