tesi R. Miscioscia.pdf - EleA@UniSA

92 Chapter 3
figure 7: Output characteristics of PI device after thermal annealing (dotted: experimental; line:
model fitting simulations with MOS ideal model).
For PS and PR samples, the same characterization steps before and
after annealing have been carried-out. For PS, the fitting results have
shown in both conditions (see figure 8 and figure 9) the presence of a
contact barrier voltage (VC), as also reported in [11]. In this case, the
undesired current affects the characteristics at low VDS and the fittings
show a dependence from the only VGS bias, which can be modeled by
IG~VGS 4 (as in eq. 2) due to Trap-Charge-Limited Space-Charge-
Limited-Current (TCL SCLC). In this case, we detected the presence
of a Source-Drain contact barrier, modeled in eq. 2 through the VC
voltage shift of the VDS as suggested by Horowitz [11].
2 4
[ ] − V
eq. 2 = −K
( V −V
)( V −V
) − ( V −V
)
I S 2 GS T DS C DS C α SG
Here, the baking treatment decreases the non-ideality factor α but
keeps the same power law exponent, as appears from fittings shown in
figure 9 with the eq. 2 model.