Superconducting Technology Assessment - nitrd

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The panel believes that the most cost effective five-year roadmap is development and establishment of the SCE chip processes at a single site, perhaps even a single facility originally sized for the final process capability but initially facilitized for the early pilot process requirements. Consideration for copying the manufacturing process exactly to a second source once the volume and/or business requires it, should be designed into the contract or other legal charter establishing the first facility. Finally, while establishment of the IC chip manufacturing capability can be accomplished at a government, academic, or industrial location, it is desirable that this facility to provide for both the future commercial business of supplying petaflops-scale computing system manufacturers with IC chips and supplying other commercial and R&D applications. This would require a strong industrial component, with government oversight derived from the contractual arrangement established for development. The most likely structure is to have a partially, or wholly, government-owned facility, managed and manned by a contractor, with commercial uses offsetting the government’s costs. Figure 4.6 shows a roadmap that takes all of these elements into account. The most cost-effective 5-year roadmap is to develop and establish the SCE chip process at a single facility partially or wholly government owned but managed and manned by a contractor. As Figure 4-6 illustrates, there are three major elements to the establishment of a superconductive IC chip manufacturing capability for petaflops-scale computing. The first is the establishment of an early pilot line capability in the most aggressive process that still allows early availability of IC chips. Until the first wafer lots are available in this process, development of concepts in CAD, micro-architecture, and circuit design could be accomplished by gaining access to the NEC process, which is the most advanced in the world . Second, in parallel with the pilot line, facilities and equipment for higher volume production in more aggressive design rules need to be started, as this element will take a substantial lead time before it is available to a program. Once both the pilot line and the manufacturing line are established, processes developed in the pilot line will be transitioned to the manufacturing line. As newer processes become well established, older processes will be phased out, first in the pilot line, then in the manufacturing line. A set of parametric and yield evaluation vehicle IC chips will be developed and held in common for the two lines. In the model shown in Figure 4-6, all development occurs in the pilot line. If co-located, the two lines could share certain equipment (such as lithography) but would require separate equipment for elements where changing process conditions might jeopardize yield. Using the cluster tool mode of fabrication would minimize redundancy and costs and allow flexibility in assignment of pilot versus manufacturing roles. The third element is the required support for the IC chip processing. Its two major elements are: ■ ■ Testing and screening of parametric and other process control IC chips, as well as yield and functional testing. Packaging of IC chips for delivery to the design development and demonstrations of capability. 91
ELEMENT 2006 2007 2008 2009 2010 Pilot Line 1st Gen Process 2nd Gen Process Establish Facility Prelim Des. Rules Proc. Elements Est. 1st Wafer Lots Proc. Qualified Prelim Des. Rules Proc. Elements Est. 1st Wafer Lots Phase Out Proc. Qualified 1st Wafer Lots 3rd Gen Process Process Control Monitor 1(PCM1) Prelim Des. Rules Proc. Elements Est. Verification Vehicles Std. Eval. Vehicle 1 (SEV1) PCM2 SEV2 PCM2 SEV2 Manufacturing Line 1st Gen Process Establish Facility Transfer to Volume Process Phase Out 2nd Gen Process Transfer to Volume Process Support Activities Screening Low Volume Chip Screening Cryo Wafer Screening Mfg Volume Screening Packaging 1.25” Carriers Demo Carriers Figure 4-6. Timeline for development of SCE manufacturing capability. 4.6.2 ROADMAP AND FACILITIES STRATEGY – MANUFACTURING FACILITIES Manufacturing RSFQ IC chips of the required complexity and in the required volumes for petaflops-scale computing will require investment, both recurring and nonrecurring. The recurring costs are associated with operation of the fabrication facility, tool maintenance, and accommodation of new tools. These include the costs of staffing the facility. The nonrecurring costs are mainly associated with the procurement cost of the fabrication tools and one-time facilities upgrades. Comparison with the SIA roadmap suggests that 1992 semiconductor technology is comparable to that needed for petaflops. Advanced lithography tools, such as deep-uv steppers, will provide easy transition to sub-micron feature sizes with excellent alignment, resolution, and size control. CMP for both oxides and metals will be important as the number of interconnects increase and feature sizes decrease. Timely procurement of the tools will be necessary to achieve the technology goals in the time frame indicated. At present, there are no true production lines for SCE chips anywhere in the world. In discussing the required manufacturing facilities, the panel assumed a baseline process with 0.8 µm diameter, 20 kA/cm 2 , 5 Nb wiring layers, and 1,000,000 JJs/chip. In such a facility, SCE IC chip production is expected to fall between 10,000 and 30,000 KGD per year. 92
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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CRYOGENIC ENVIRONMENT High-speed ne
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■ ■ Chalmers University in Swed
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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The major issue to be addressed wil
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: TABLE 3.1-1. PUBLISHED SUPERCONDUCT
Page 60 and 61: S G G Chip-side microstrip S Carrie
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103: TABLE 4-9. SCALING REQUIREMENTS FOR
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: TABLE 5-1. I/O TECHNOLOGIES FOR PET
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: TABLE 6-2. MCM FABRICATION TOOLS AN
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
Page 139 and 140: Another issue is the cost of the re
Page 141 and 142: Some of the thermal and electrical
Page 143 and 144: Optical interconnects may require t
Page 145 and 146: 6.6.4 SYSTEM INTEGRITY AND TESTING
Page 147 and 148: Appendix A
Page 149 and 150: ■ ■ ■ ■ Construct a detaile
Page 151 and 152: Appendix B
Page 153 and 154: GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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