Superconducting Technology Assessment - nitrd

The bandwidth, chip density and interconnect distance requirements place multi-chip modules (MCM) as the leading
candidate technology for large SCE-based systems. The MCM requirements include:
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Use of niobium wiring for the dielectric portion of the MCM (MCM-D).
A combination ceramic and dielectric MCM (MCM C+D) technology.
Low impedance transmission lines.
The MCM is projected can hold 50 chips on a 20 cm X 20 cm substrate and pass data at 32 Gbps (Figure 2). It will
have multiple wiring layers (up to nine superconductor wires), separated by ground planes and will need to
accommodate different impedance wiring. To date, 20 SCE chips have been attached to an MCM of this type, each
chip with 1,360 bumps.
Figure 2. A multi-chip module with SCE chips(left, NGST‘s Switch chip MCM with amplifier chip; center, NGST’s MCM; right, HYPRES’ MCM).
Although MCMs with SCE chips are feasible, the signal interface and data links impose further challenges. The
large number of signal channels and high channel densities is difficult to achieve for two reasons:
1. The signals pass from the chips into the MCM layers within the area constraints of the pad
geometry (maximum connection density for this process is dominated by via diameter and via
capture pad area).
2. The MCM must transport signals laterally between chips and to peripheral connectors
(maximum density for lateral signal transmission is determined by the wiring pitch and the
number of layers).
1) Chip-to-MCM I/O: The issues for the die attach are the pin-out density (2 k to 5 k signal pads per chip), and the
inductance (< 10 pH) and bandwidth requirements (>50 Gbps). The leading candidate for the chip-to-MCM attach
is flip-chip bonding utilizing solder reflow connections. This attach method allows for both high interconnect
densities as well as the low-inductance connections required for 32 Gbps data transmission. Figure 3 gives
interconnect inductance as a function of bond length or height for different types of interconnects. Other candidate
technologies typically suffer from either insufficient interconnect densities or relatively large inductances which limit
data rates to less than 10 Gbps.
A data rate of 32 Gbps between chips appears feasible using appropriate superconductor driver and receiver
circuits. Bandwidth is limited by a L/R time constant, where L is the inductance of the chip-to-MCM bump and R
is the impedance of the microstrip wiring. For reasonable values of L (3-10 pH) and R (10-20 Ω), the cutoff
frequency is in the THz regime.
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