Superconducting Technology Assessment - nitrd

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3.1.5 RSFQ PROCESSORS – ISSUES AND CONCERNS Identifying and addressing important issues early will reduce the risk for demonstration of a high-performance RSFQ processor. TABLE 3.1-6. ISSUES FOR RSFQ PROCESSOR TECHNOLOGY DEVELOPMENT AND RESOLUTION Issue – Margins are impacted by parameter spreads, gate optimization, current distribution cross-talk, signal distribution cross-talk, noise, bias and ground plane currents, moats and flux trapping, and timing jitter. – Shrinking margins have recently been reported for large circuits (>10 3 JJ’s) for clock rate above 10 GHz. Resolution – Isolate on-chip power bus and data lines from gate inductors by additional metal layers. – Control on-chip ground currents by using differential power supply. – Optimize design for timing. – Low gate density. – Improve litho to shrink features. – Increase number of superconducting layers so power, data transmission lines, and gates are on separate levels. – Clock skew. – On-chip velocity ~100µm/ps. – At 50 GHz, distance within clock cycle is 2 mm. – Increase gate density to reach more gates in clock cycle. – Generate clock on-chip. – Resynchronize local clocks. – Timing tolerant design and microarchitecture. – Thermal and environmental noise increases errors. – All I/O lines are subject to noise pickup and cross-talk. – Reduce environmental noise by isolating and filtering. power and I/O lines. – Timing errors limit clock frequency. – All junctions contribute jitter. – Noise enhances jitter. – Reduce environmental noise. – Reduce number of JJs in data and clock. distribution network. – Improve timing analysis and simulation using VHDL. – Magnetic flux trapped in superconducting films can shift the operating point of devices. – Local magnetic field and large transients sources of trapped flux. – Improved shielding and filtering. – Develop methodology for design of moats to trap magnetic flux away from circuits. – Dense chips require many amperes of current. – Supply RF bias-current from RT to ~40 K. – RF-DC power converter at ~ 40 K. – Use HTS power leads from 40 to 4 K. – Extensive current reuse on chip and between chips. – No vendor for superconducting MCM. – Decision between internal or vendor development. Appendix G: Issues Affecting RSFQ Circuits provides an expanded discussion of these topics. (The full text of this appendix can be found on the CD accompanying this report.) 51
3.1.6 RSFQ PROCESSORS – PROJECTED FUTURE CAPABILITY Chip density is a major factor in the ultimate success of RSFQ technology in HEC, and in many other nascent applications. Comparing present 1-µm RSFQ technology with 0.25-µm CMOS that has many more wiring layers, the panel can draw general conclusions about RSFQ density limits. As described further in Chapter 4, the last Northrop Grumman process could be extended to 1 million JJs/cm 2 in one year with a few readily achievable improvements in the fabrication process. This does not imply that 1 million JJs/cm 2 is the limit of RSFQ technology; greater density would be achieved from further advances in fabrication, design, and innovative concepts. For example, self-clocked circuits without bias resistors is one concept that would reduce power and eliminate the separate clock distribution circuitry, thereby reducing clock jitter and increasing gate density. The panel foresees multi-level circuit fabrication multiplying the functionality of chips as another step forward. 3.2 MEMORY Cryogenic RAM has been the most neglected superconductor technology and therefore needs the most development. The panel identified three attractive candidates that are at different stages of maturity. In order of their states of development, they are: ■ ■ ■ Hybrid JJ-CMOS RAM. Single-flux-quantum superconductive RAM. <strong>Superconducting</strong>-magnetoresistive RAM (MRAM). To reduce risk, the panel concluded that development should commence for all three, with periodic evaluation of progress and relative investment. It is essential that the first-level memory be located very close to the processor to avoid long time-of-flight (TOF) delays that add to the latency. The panel evaluated options for cryo-RAM, including the critical first-level 4 K RAM that could be located on an MCM adjacent to the processor. Table 3.2-1 compares these memory types. TABLE 3.2-1. COMPARISON OF READINESS AND CHARACTERISTICS OF CANDIDATE CRYOGENIC RAM Memory Type Readiness for Investment Potential Density Potential Speed Potential Power Dissipation Cost ($M) Hybrid JJ-CMOS High High Medium Medium 14.2 SFQ Medium Medium Medium-high Low-medium 12.25 MRAM (40 K) Medium High Medium Medium SC-MRAM (4K) Low High High Low 22 Monolithic RSFQ-MRAM Very low High Very high Very low Total Investment 48.45 52
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: CRYOGENIC ENVIRONMENT High-speed ne
Page 29 and 30: ■ ■ Chalmers University in Swed
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: The major issue to be addressed wil
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: TABLE 3.1-1. PUBLISHED SUPERCONDUCT
Page 60 and 61: S G G Chip-side microstrip S Carrie
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: TABLE 4-9. SCALING REQUIREMENTS FOR
Page 105 and 106: ELEMENT 2006 2007 2008 2009 2010 Pi
Page 107 and 108: A potential savings of ~40% in the
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Page 111 and 112: TABLE 5-1. I/O TECHNOLOGIES FOR PET
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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