Superconducting Technology Assessment - nitrd

Issues
The HTMT RSFQ-related design work focused on the following issues:
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A multithreaded processor architecture that could tolerate huge disparities between
the projected 50-60 GHz speed of RSFQ processors (called SPELL) and the much slower
non-superconductor memories located outside the cryostat; and
The projected characteristics of the RSFQ superconductor petaflops subsystem consisting
of ~4,000 SPELL processors with a small amount of superconductor memory (called CRAM)
and the superconductor network for inter-processor communication.
Chip Design
The architecture of SPELL processors was designed to support dual-level multithreading with 8-16 multistream units
(MSUs), each of which was capable of simultaneous execution of up to four instructions from multiple threads
running within each MSU and sharing its set of functional units. However, no processor chip design was done for
SPELL processors; their technical characteristics are only estimates based on the best projection of RSFQ circuits
available at that time (1997-1999).
2.2.2 20-GHZ, 8-BIT FLUX-1 MICROPROCESSOR (2000-2002)
The 8-bit FLUX-1 microprocessor was the first RSFQ microprocessor designed and fabricated to address architectural
and design challenges for 20+ GHz RSFQ processors. The FLUX-1 design was done in the framework of the FLUX
project as a collaboration between the SUNY Stony Brook, the former TRW (now Northrop Grumman Space
Technology), and the Jet Propulsion Laboratory (NASA).
New Microarchitecture Development
A new communication-aware partitioned microarchitecture was developed for FLUX-1 with the following
distinctive features:
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Ultrapipelining to achieve 20 GHz clock rate with only 2-3 Boolean operations per stage.
Two operations per cycle (40 GOPS peak performance for 8-bit data).
Short-distance interaction and reduced connectivity between Arithmetic Logic Units (ALUs)
and registers.
Bit-streaming, which allows any operation that is dependent on the result of an
operation-in-progress, to start working with the data as soon as its first bit is ready.
Wave pipelining in the instruction memory.
Modular design.
~25 control, integer arithmetic, and logical operations (no load/store operations).
Chips
The final FLUX-1 chip, called FLUX-1R chip, was fabricated in 2002. It had 63,107 Josephson junctions (JJs) on a
10.35 x 10.65 mm 2 die with power consumption of ~ 9.5 mW at 4.5 K.
Operation of a one-bit ALU-register block (the most complex FLUX-1R component) was confirmed by testing.
No operational FLUX-1R chips were demonstrated by the time the project ended in 2002.
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