Superconducting Technology Assessment - nitrd

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3.3 CAD TOOLS AND DESIGN METHODOLOGIES A CAD suite that enables a competent engineer who is not a JJ expert to design working chips is essential to demonstrate the readiness of RSFQ processor technology described in Section 3.1. Presently available software is satisfactory only for modest-size circuits of a few thousand JJs, and CAD functions unique to superconductive circuits are poorly supported. Today the superconductor industry primarily uses the Cadence environment, augmented by custom tools. Stony Brook University has developed custom programs, including a device-level circuit simulator and an extractor of inductance from the physical layout. The University of Rochester has moved superconductive IC design to the Cadence software environment. However, the custom tools are poorly supported by the commercial vendor, if at all, and significant investment will be necessary to integrate the superconductive electronics (SCE) tools to arrive at a maintained CAD suite that will support VLSI-scale circuit design. CAD capability needs to advance to support an increase in integration scale from a few thousand to millions of JJs: ■ ■ ■ ■ Inductance extraction must be extended to sub-micron wires. Device and noise models must be extended to sub-micron JJs. Transmission line models must be extended to the high frequency regime. VHDL models and methods must be extended to larger integration scale and more complex architectures. Status In the last decade, superconductive RSFQ digital electronics has grown in size and complexity as it has moved from academic research toward applications development. Initially, only a few experts could successfully design circuits of significant functionality. Two examples of what has been achieved are the line of HYPRES A/D converters, including the 6,000 JJ design pictured in Figure 3.3-1 and the Japanese-developed microprocessor shown in Figure 3.3-2. The technology is now accessible to a wider group of designers, due primarily to the introduction of standard design methodology and industrial CAD tools. 67
Figure 3.3-1. ADC chip containing about 6,000 JJs was developed by HYPRES. This integration scale can be achieved by experts in the field using design rule checking (DRC) CAD verification. Figure 3.3-2. A bit-serial superconductor microprocessor featuring 6,300 JJs, 7 instructions, and a 16 GHz clock. The circuit was developed and tested by an independent consortium of Japanese universities. Readiness The IC design software developed by Stony Brook University and the University of Rochester was integrated into a single suite at Northrop Grumman. The readiness of U.S.-based design methodology and CAD tools is described below using the Northrop Grumman capability as an example. While built upon the academic projects, it also leverages the methodology and software that serves the commercial semiconductor ASIC world. A significant challenge for fabrication at or below the 0.25-micron node is the development of inductance extraction software that is accurate for smaller features. Cadence supports extraction of device parameters from the physical layout. However, extraction of inductance values is not well-supported. New software should use 3-dimensional modeling of magnetic fields to accurately predict the inductance of sub micron lines. Hardware Description Language (HDL) models need to contain the right information, such as gate delay as a function of the parasitic inductive load associated with the physical wiring between gates. Standards for gate models exist, such as standard delay format in which gate delay is given in terms of nominal, typical high, and typical low values of physical parameters. VHDL has been used in the design of such complex multichip superconductive digital systems such as Northrop Grumman’s programmable bandpass A/D converter that combined mixed signal, digital signal processing, and memory elements. The same schematic used to design the circuit in VHDL can be used for layout-versus-schematic (LVS) verification. By combining process control monitor and visual inspection data to characterize each die on the foundry side with CAD verification on the designers side, first-pass success had become routine for chips of up to a few-thousand JJs fabricated in the Northrop Grumman foundry. 68
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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CRYOGENIC ENVIRONMENT High-speed ne
Page 29 and 30: ■ ■ Chalmers University in Swed
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: The major issue to be addressed wil
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: TABLE 3.1-1. PUBLISHED SUPERCONDUCT
Page 60 and 61: S G G Chip-side microstrip S Carrie
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: TABLE 4-9. SCALING REQUIREMENTS FOR
Page 105 and 106: ELEMENT 2006 2007 2008 2009 2010 Pi
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: TABLE 5-1. I/O TECHNOLOGIES FOR PET
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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