Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
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Various moat protocols have been proposed and tried: long narrow channels, an array of circular holes, and random<br />
sizes and shapes. Studies at NEC and UC Berkeley concluded that long, narrow moats surrounding each gate are<br />
best, particularly if the area enclosed by the moat is smaller than the area of one flux quantum in the ambient field.<br />
However, moats cannot fully surround a gate because that would require wideband data lines to cross a region<br />
without a ground plane. Therefore, moats have breaks.<br />
For a high probability of trapping flux in the moat, the moat inductance should be large to minimize the energy<br />
require to trap the flux. Thus, E SFQ = Φ 02<br />
/2L moat should be small. Narrow moats increase packing density, but have<br />
low inductance per unit length; long moats increase inductance. Therefore, long, narrow moats appear to be the<br />
best option. When flux is squeezed into the moat, it creates a corresponding shielding current in the surrounding<br />
superconducting film. Just as ground-plane currents are not confined either under a microstripline or to the edge<br />
of the ground plane, the shielding currents surrounding a moat are not confined to a London penetration depth<br />
from the edge of the moat. They are spatially distributed on the ground plane as required to meet the boundary<br />
condition that the normal component of magnetic field is zero. Assuming the length factor for shielding ground<br />
currents is approximately the width of the moat, the moat should be as narrow as litho permits and at least one<br />
width’s distance removed from the nearest circuit inductor.<br />
A second source of trapped flux is the equivalent of ESD in semiconductors. Transient signals that are not well<br />
filtered in any lead can produce trapped flux in the superconducting films and shift operating margins. The solution<br />
here is to employ isolation techniques in addition to filtering, including optical isolators in input/output lines and<br />
transmitting bias current to the shielded cryogenic environment by narrow band filtered RF.<br />
Chips are usually flipped and bonded to a substrate with a superconducting film directly below the chip. This brings<br />
the active circuits at most a few microns from another superconducting ground plane. Although there is no data<br />
that supports this conjecture, one should be concerned and it needs to be addressed. EM simulations should help,<br />
but it will have to be resolved experimentally.<br />
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