Superconducting Technology Assessment - nitrd

4.3 SCE CHIP FABRICATION FOR HEC – READINESS
Implementation of SCE for petaflops computing will require three circuit types: logic, cryogenic memory, and network
switches. For the HTMT petaflops project, it was estimated that 4,096 processors, comprised of 37K SCE IC chips
containing a total of 100 billion JJs and partitioned on 512 MCMs, would be required. Manufacture of such a large-scale
system will require significant advances in SCE IC chip fabrication.
The two key advantages of superconductive RSFQ technology for petaflops-scale computing are ultra-high on-chip
clock speeds (50-100 GHz or greater) and ultra-low power dissipation (nanowatts per gate). However, while the
status presented in the previous section shows the enormous promise of RSFQ technology, significant improvements
in density and clock speed of chips are required for petaflops computing. In order to produce petaflops processor
elements with a practical chip count per element (~10-15), the RSFQ logic chip will have an estimated 12 million,
0.5 - 0.8 µm diameter junctions and 5 - 7 wiring layers on a die no larger than 2 cm x 2 cm. Junction current density
must be increased to provide higher circuit speeds (circuit speed increases as the square root of the J c increase).
Scaling present-day Nb IC chip technology to produce the necessary circuits will require:
■ A major increase in circuit density (from