Superconducting Technology Assessment - nitrd

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SFQ RAM Status The results of five completely superconductive RAM projects are summarized in Table 3.2-4. TABLE 3.2-4. SUPERCONDUCTIVE RAM PROJECTS Organizations Project Parameter Comments ISTEC-SRL – RSFQ decoder activates latching drivers, which – 256 bits. – 3747 JJ. – Planned 16 kb of 64 blocks on 2.5cm 2 . address SFQ memory cells. – 1.67 mW@ 10kHz. – 107 mW for 16 kb. – VT cells. – 2.05mmx1.87mm. – SRL 4.5 kA/cm 2 process. – Discontinued. Northrop – RSFQ input/output. – Speed > 1 GHz expected, – Decoder tested @ 0.5 GHz. Grumman – NEC VT cells. – Latching driver impedance limited by TOF. – 16 kb on 1-cm 2 chip in – 1 kb RAM with address. line and sense amplifiers matched to word 2 kA/cm 2 process. partially tested. transmission line for BW. – Incomplete. – 6 x 6 array tested at low speed, 1-cell @0.5 GHz. HYPRES – CRAM. – Long junctions used. – 16 kb design used – Pipelined DC powered – 400ps access, 100ps cycle 4 4kb subarrays. SFQ RAM. time estimated. – 4 kb block tested at low speed. – 16 kb on 1-cm 2 . – Due to block pipeline, time – Power estimated @ 8 mW for 64-kb RAM scales as: 600ps for 16 kb. access, ~100ps cycle time. – Density increase, cycle time reduced to 30ps, access time ~400ps projected with 20kA/cm 2 . – Discontinued at end of HTMT project. Stony Brook University – RAM with SFQ access. – Read pulse travels on active line of JTL/cell stages. – Developed SFQ cell and decoder for 1kb RAM. – Problem is strong content dependence affected operation. Northrop – Ballistic RAM (BRAM). – SFQ pulses propagate through – Simulated SFQ signals passed Grumman – Cells are 1-JJ, 1-inductor. – SFQ pulses not converted bit lines and are directly detected at end of bit line. through series of 64 cells in ~50ps to simulate read. to voltage-state drive levels. – Bit lines are controlled impedance – Decoder delay estimated at 40ps. passive transmission lines. – DRO cells so refresh must – Waveform generated on word be accommodated. line couples ~50mA to each cell in row. 57
In summary, several ideas have been studied. In two of these, the memory cells were the NEC vortex transitional (VT) type cells, which were developed for use with voltage-state logic and require voltage-state drivers. One design provided for SFQ input and output pulses on a 256-bit array with potential for high speed. However, scaled to 64 kb, this array would have untenable power dissipation and large size. The other group did not demonstrate a complete system. The cryo-RAM (CRAM) developed at HYPRES had attractive estimated access and cycle times for 4-kb blocks, but no high-speed data. The estimates for power and access and cycle times scaled to 64-kb are attractive. Circuit density and cycle and access times would be more favorable with increased current density. The ballistic RAM (BRAM) is an interesting concept that will require more research. For all, more advanced fabrication would lead to greater circuit density. SFQ RAM Readiness for Investment Although SFQ RAM technology is not as advanced as hybrid CMOS, the panel feels that very attractive concepts exist and should be investigated to support RSFQ processors for HEC. An effort should be made to further evaluate the CRAM and BRAM in order to project their advantages and disadvantages and to quantify power, access time, density, and probability of success. The panel urges that the better choice be pursued at least to the bit-slice stage to further define the key parameters. If successful, the development should be completed. SFQ RAM Projections The CRAM design should be scaled to a 20 kA/cm 2 process and 64-kb RAM to determine the important parameters of speed, power, and chip size. The BRAM concept will require more design evaluation to determine its potential, but either of these ideas could have advantages over the hybrid Josephson-CMOS memory in speed and power. As noted for the hybrid memory, memory chip design will require close collaboration between the architecture and memory teams in order to find the best processor-memory communication and internal memory chip organization to meet the read/write latency, access cycle time, and bandwidth requirements of 50 GHz processors. SFQ RAM Issues and Concerns As in any large RSFQ circuit, margins and flux trapping may be problems. The testing of the CRAM was only done at low speed, so new issues may arise when operated at high speed. In the present DRO BRAM concept, methods for refreshing will have to be explored in order to retain the beneficial aspects of this memory. SFQ RAM Roadmap TABLE 3.2-5 SFQ RAM ROADMAP AND INVESTMENT PLAN Milestone Year Cost ($M) Design 64-kb CRAM and BRAM and design bit slice for test and evaluation Test and evaluate bit slice Design, test, and evaluate complete 64 kb memory Interface memory with processor Integrate memory with processor; Test and evaluate Total Investment 2006 2007 2008 2009 2010 2.45 2.45 2.45 2.45 2.45 12.25 58
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: CRYOGENIC ENVIRONMENT High-speed ne
Page 29 and 30: ■ ■ Chalmers University in Swed
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: The major issue to be addressed wil
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: TABLE 3.1-1. PUBLISHED SUPERCONDUCT
Page 60 and 61: S G G Chip-side microstrip S Carrie
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 78 and 79: MRAM Major Issues and Concerns Mate
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: TABLE 4-9. SCALING REQUIREMENTS FOR
Page 105 and 106: ELEMENT 2006 2007 2008 2009 2010 Pi
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: TABLE 5-1. I/O TECHNOLOGIES FOR PET
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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