Superconducting Technology Assessment - nitrd

All IC chips on completed wafers undergo room temperature testing prior to dicing. Process control monitor (PCM)
chips are mounted on superconductive multi-chip modules (MCMs) tested at 4 K. These Nb-based MCMs are produced
in the main fabrication facility, while MCMs for product IC chips are produced separately. (MCM fabrication and
testing is discussed in Chapter 6.)
The fabrication group:
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Maintains a database of PCM data and is responsible for its analysis, which provides
the basis for the process design rules.
Maintains the gate library, which is developed in collaboration with the circuit design
group(s); is responsible for incorporating circuit designs into mask layouts and for
procuring photolithographic masks.
Produces IC chips for verification of CAD, gates, designs, IC chip architectures, and all
IC chips required for the demonstrations associated with this program.
Potentially can provide foundry services for other digital SCE programs (government,
academic, or commercial).
4.2 DIGITAL SUPERCONDUCTIVE IC CHIP FABRICATION – STATUS
Fabrication of superconductive ICs is based on semiconductor wafer processing, using tools developed for CMOS
processing or customized versions of these tools. However, the process flow is much simplified from that of CMOS,
with only metalization or insulator deposition steps, followed by patterning of these layers by etching. Figure 4-2
shows a simplified flow, along with a photo of a superconducting foundry (one tunnel).
SIMPLE 3-STEP SCE FAB PROCESS
Layer by Layer
Circuit Designs
Photographic Plates
Typical 200 mm
SCE Wafer
Deposit thin
oxide or
metal film
Photographically
transfer pattern
to wafer
Etch pattern
into film
Repeat for each plate
a) Simple process flow for fabrication of RSFQ circuits b) RSFQ fabrication facility
Figure 4-2. Fabrication of RSFQ ICs is accomplished using semiconductor equipment and processes.
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