Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
Superconducting Technology Assessment - nitrd
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6.5 POWER DISTRIBUTION AND CABLES<br />
<strong>Superconducting</strong> processor chips are expected to dissipate very little power. The cryocooler heat load for a<br />
petaflops system will be dominated by heat conduction through input/output (I/O) and power lines running<br />
between low and room-temperature environments. To reduce heat load, it would be desirable to make the lines<br />
as small as possible in a cross section. However, requirements for large DC power supply currents and low-loss,<br />
high bandwidth I/O signaling both translate into a need for a large metal cross section in the cabling for low<br />
signal losses and low Joule heating. Therefore, each I/O design must be customized to find the right balance<br />
between thermal and electrical properties.<br />
SCE circuits for supercomputing applications are based on RSFQ circuits that are DC powered. Due to the low<br />
voltage (mV level), the total current to be supplied is in the range of few Amperes for small-scale systems and can<br />
be easily kilo-Amperes for large-scale systems. Serial distribution of DC current to small blocks of logic has been<br />
demonstrated, and this will need to be accomplished on a larger scale in order to produce a system with thousands<br />
of chips. However, the overhead of current-supply reduction techniques on-chip can be expected to drive the<br />
demand for current supply into the cryostat as high as can be reasonably supported by cabling.<br />
In addition, because petaflops systems will have very high I/O rates, Radio Frequency (RF) cabling, which can support<br />
high line counts serving thousands of processors with high signal integrity, is needed. Reliable cable-attach<br />
techniques for thousands of connections also require cost efficient assembly procedures with high yield.<br />
6.5.1 POWER DISTRIBUTION AND CABLES – STATUS<br />
Supplying DC current to all of the SCE chips in parallel would result in a total current of many kiloAmps. Several<br />
methods may be used to reduce this total current and heat load. One technique is to supply DC current to the SCE<br />
chips in series, rather than in parallel (known as current recycling). This technique of providing DC current to RSFQ<br />
has been demonstrated, but there is real estate and junction count overhead associated with this method. This overhead<br />
will drive system design to find a high DC current “comfort zone” for the power supply.<br />
Another solution is to use switching power supplies. High voltages/low currents can be brought near SCE circuits<br />
and conversion to low voltages/high currents, all at DC, can occur at the point of use. However, this method<br />
employs high power field-effect transistor switches, which themselves can dissipate significant power.<br />
If sufficient cooling power is available at the intermediate cryogenic temperature (such as 77 K), then high temperature<br />
superconductor (HTS) cables may be used to bring in DC current from 77 K to the 4 K environment. High temperature<br />
stranded DC cabling is a well known product, but there has been little demonstration of flexible ribbon cabling in<br />
HTS—the most desirable implementation for a large system such as a petaflops computer—where the component<br />
count and number of connections makes reliability, modularity, and assembly very difficult with individual cable.<br />
For serial I/O in systems with low I/O counts, coaxial cables can be used for both high-speed and medium-speed<br />
lines. These cables are made in sections, with a middle section having a short length of stainless steel having a high thermal<br />
resistance, and with a bottom section of non-magnetic Copper for penetration into the chip housing.<br />
For systems with hundreds or thousands of I/O lines, coaxial cables are not practical. To meet this challenge,<br />
flexible ribbon cables have been developed 8 (Figure 6-7). These cables consist of two or three layers of copper<br />
metallization separated by dielectric films, typically polyimide. With three copper layers, the outer two layers serve<br />
as ground planes and the inner layer forms the signal lines, creating a stripline configuration. Stripline cables<br />
provide excellent shielding for the signal lines. Successful high-reliability and low cost cable-attach procedures for<br />
signals up to 3 GHz have been demonstrated, and this technique should allow operation up to 20GHz after minor<br />
modifications. Present flex cable line density is sufficient for the MCM-to-MCM connections, but is an order of<br />
magnitude lower than required for the external I/O.<br />
8<br />
“Cryogenic Packaging for Multi-GHz Electronics” T. Tighe et al, IEEE Tran. Applied Superconductivity, Vol 9 (2), pp3173-3176, 1999.<br />
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