Superconducting Technology Assessment - nitrd

SYSTEM INTEGRATION
System integration is a critical but historically neglected part of the overall system design. Superconductive
electronic (SCE) circuits offer several challenges due to their extremely high clock rates (50-100 GHz) and ability to
operate at extremely cold temperatures. The ultra-low power dissipation of Rapid Single Flux Quantum (RSFQ) logic
means that a compact package can be used, enabling high-computational density and interconnect bandwidth. The
enclosure must also include magnetic and radiation shielding needed for reliable operation of SCE circuits.
System integration for large-scale SCE systems was investigated in previous programs such as HTMT 1 , whose
approach is shown in Figure 6.1. In this concept, the cryogenic portion of the system occupies about 1 m 3 with a
power load of 1 kW at 4 K. Chips are mounted on 512 multi-chip modules (MCM) that allow a chip-to-chip bandwidth
of 32 Gbps per channel. Bisectional bandwidth into and out of the cryostat is 32 Pbps.
The major components of this system concept are:
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Chip-level packaging including MCMs, 3-D stacks and boards.
Cables and power distribution hardware.
System-level packaging including enclosures and shields, refrigeration unit, system integration and test.
A) B)
Figure 6.1. A) System installation concept for petaflops HTMT system. Enclosure for the superconducting processors is 1 m 3 white structure
with cooling lines into the top. B) Packaging concept for HTMT SCP, showing 512 fully integrated multi-chip modules (MCMs) connected to
160 octagonal printed circuit boards (PCBs). The MCMs, stacked four high in blocks of 16, are connected to each other vertically with the use
of short cables, and to room temperature electronics with flexible ribbon cables (I/Os). The drawing has one set of the eight MCM stacks missing,
and only shows one of the eight sets of I/O cables.
1
HTMT Program Phase III Final Report, 2002
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