Superconducting Technology Assessment - nitrd

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GLOSSARY TERMS/DEFINITIONS BER CDR CMOS CNET CRAM DARPA DoD DRAM FLOPS FLUX Gb Gbps GB GFLOPS GHz HEC HECRTF HPCS HRAM HTMT IBM IC Bit Error Rate Critical Design Review Complementary Metal Oxide Semiconductor Cryostatic NETwork Cryogenic RAM Defense Advanced Research Projects Agency Department of Defense Dynamic RAM. Has relatively slow access time—in the tens of nanoseconds—but high memory density. Floating Point Operations Per Second. Used as a unit of performance. Not an acronym. This is the name of a series of superconducting electronics VLSI experiments. Gigabit Gigabit per second GigaByte GigaFLOPS Giga Hertz—one billion times per second High-End Computer High-End Computing Revitalization Task Force High Productivity Computing Systems Holographic RAM Hybrid Technology Multi-Threaded architecture International Business Machines Integrated circuit or “chip” 143
TERMS/DEFINITIONS IHEC LLNL JJ JPL JTL kW MCM mW MW MOS MRAM NASA NGST NSA NSF NRZ Integrated High End Computing; a congressionally-mandated R&D Plan Lawrence Livermore National Laboratory Josephson junction Jet Propulsion Laboratory Josephson Transmission Line kilowatt(s) Multi-Chip Module milliwatts(s) megawatt(s) Metal Oxide Semiconductor Magnetoresistive Random Access Memory National Aeronautics and Space Administration Northrop Grumman Space Technology National Security Agency National Science Foundation Non-Return to Zero peta Prefix meaning 10 15 PCB PFLOPS PIM RAM RF RSFQ R&D SCE SFQ Printed Circuit Board PetaFLOPS Processor In Memory. A hardware architecture in which both processing logic and memory are placed on the same IC. The principle advantage is to allow direct access to a row (usually 2048 bits) at a time. Random Access Memory Radio Frequency Rapid Single Flux Quantum Research and Development Superconducting Electronics Single Flux Quantum 144
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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CRYOGENIC ENVIRONMENT High-speed ne
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■ ■ Chalmers University in Swed
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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The major issue to be addressed wil
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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TABLE 3.1-1. PUBLISHED SUPERCONDUCT
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S G G Chip-side microstrip S Carrie
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
Page 105 and 106: ELEMENT 2006 2007 2008 2009 2010 Pi
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: TABLE 5-1. I/O TECHNOLOGIES FOR PET
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: TABLE 6-2. MCM FABRICATION TOOLS AN
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
Page 139 and 140: Another issue is the cost of the re
Page 141 and 142: Some of the thermal and electrical
Page 143 and 144: Optical interconnects may require t
Page 145 and 146: 6.6.4 SYSTEM INTEGRITY AND TESTING
Page 147 and 148: Appendix A
Page 149 and 150: ■ ■ ■ ■ Construct a detaile
Page 151 and 152: Appendix B
Page 153 and 154: GOVERNMENT George Cotter Director f
Page 155: Appendix C
Page 159 and 160: Appendix D
Page 161 and 162: The time-dependent behavior of this
Page 163 and 164: RSFQ electronics is faster and diss
Page 165 and 166: Similar to CMOS, the irreducible po
Page 167 and 168: Appendix E
Page 169 and 170: The report further identified four
Page 171 and 172: Analog high temperature superconduc
Page 173 and 174: Appendix F
Page 175 and 176: Only one significant effort to arch
Page 177 and 178: Execution Models Organizing hardwar
Page 179 and 180: Development Issues and Approaches T
Page 181 and 182: Appendix G
Page 183 and 184: The two-junction comparator, the ba
Page 185 and 186: Bias Currents A major cause of degr
Page 187 and 188: Power and bias current Power is dis
Page 189 and 190: Appendix H
Page 191 and 192: SMT MRAM Another direct selection s
Page 193 and 194: Speed and Density The first planned
Page 195 and 196: 120 0.10 100 Write I (mA) 0.08 0.06
Page 197 and 198: Appendix I
Page 199 and 200: Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Table 5 Reactive Ion Etch Parameter
Page 205 and 206: Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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