Superconducting Technology Assessment - nitrd

Inter-chip Communications
Driver and receiver circuits have already been demonstrated to 60 Gbps per line in the NG fabrication processes. Since
speed and bit error rate (BER) will improve as J C increases, the circuit technology is ready now. The principal task will be
to accommodate the increased number of high-data-rate lines on each chip and MCM. Shrinking bump size and minimum
spacing, better design tools, and simulation models will be important to minimize reflections and cross-talk at
both the signal and ground chip-to-MCM bumps. The crossbar switch program provides a rich experience base in the
engineering of ribbon cables. In particular, the trade-off between heat leak and signal loss is well understood.
Table 3.1-2 summarizes the readiness of superconductive circuits today and projects readiness in 2010 based on the roadmap.
TABLE 3.1-2. SUPERCONDUCTIVE CIRCUIT TECHNOLOGY READY FOR MAJOR INVESTMENT AND DEVELOPMENT
Circuit Type
2004 Readiness
Projected 2010 Readiness
Logic
– Small circuits @ lower speed.
– >10 6 JJ/cm 2 @ 50 GHz clock.
SFQ RAM
– Experimental 4 kb RAM
@ low speed.
– Analysis of SFQ ballistic RAM.
– 256 kb SFQ ballistic RAM
@ 500 ps access time.
Hybrid RSFQ-CMOS
RAM
– Experimental proof-of-concept.
– 256 kb hybrid @ 500 ps.
Monolithic RSFQ
MRAM
– RSFQ write/read
concept formulated.
– 128 kb hybrid @ 500 ps.
Vector Register, FIFO
– 32 bit FIFO @ 40 GHz.
– 4 kb FIFO @ 50 GHz.
Communication
Circuits
– Chip-to-chip @ 60 Gbps.
– 64-bit word-wide chip-to-chip
@ 50 GHz.
I/O
– 10 Gbps driver.
– 64-bit word-wide drivers @ 40 Gbps/s.
Switch
– 2.5 Gbps per port circuit
switch, scalable.
– 64-bit word wide, scalable
@ 50 Gbps per port.
In evaluating the circuit technology and projecting a high probability of success in HEC, the panel considered
the availability of VLSI fabrication. As much as anything, success in RSFQ processor development will depend on
a dedicated industrial-quality VLSI manufacturing facility that provides a significant step-up in topological design
rules and chip yield from current R&D facilities (see Chapter 4).
Cryogenic testing is much more difficult than room temperature testing. Testing at 50 to 100 GHz clock frequencies
magnifies the challenge significantly. A high-speed test bench will be required that is customized to test and evaluate
all superconductive circuits from the cell libraries through the RSFQ processor integrated with RAM, including memory
and network switches. The test bench must provide environmental support (cooling, RF and magnetic shielding),
power supplies, commercial and specialized digital test equipment, and fixturing to accommodate various device
modules. SFQ diagnostic circuits have been demonstrated and should be employed to meet the requirements of
the test plans.
48