Superconducting Technology Assessment - nitrd

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RSFQ TECHNOLOGY IS VIABLE TABLE E-2. RSFQ SUMMARY Technical Advantages Technical Challenges The most advanced alternative technology. Providing high-speed and low-latency memory. Combines high speed with low power. Ready for aggressive investment. Architecting systems that can tolerate significant memory access latencies. Providing very high data rate communications between room temperature technology and cooled RSFQ. Most Advanced Alternative Technology The ITRS 2004 update on Emerging Research Devices lists many candidate technologies, presently in the research laboratories, for extending performance beyond today’s semiconductor technology. Superconducting RSFQ is included in this list and is assessed to be at the most advanced state of any of the alternative technologies. Ready for Aggressive Investment In the opinion of the panel, superconducting RSFQ circuit technology is ready for an aggressive, focused investment to meet a 2010 schedule for initiating the development of a petaflops-class computer. This judgment is based on: ■ ■ ■ An evaluation of progress made in the last decade. Projection of the benefits of an advanced very-large-scale integration (VLSI) process for RSFQ in a manufacturing environment. A roadmap for RSFQ circuit development coordinated with VLSI manufacturing and packaging technologies. Can Leverage Semiconductor Technology Base Although RSFQ circuits are still relatively immature, their similarity in function, design, and fabrication to semiconductor circuits permits realistic extrapolations. Most of the tools for design, test, and fabrication are derived directly from the semiconductor industry, although RSFQ technology will still need to modify them. Significant progress has already been demonstrated on limited budgets by companies such as Northrop Grumman and HYPRES, and in universities such as Stony Brook and the University of California, Berkeley. High Speed with Low Power Individual RSFQ circuits have been demonstrated operating at clock rates in the hundreds of GHz, and system clocks of at least 50GHz seem quite attainable, with faster speeds possible. In addition, RSFQ devices have lower power requirements than other systems, even after cooling requirements are included. Extremely low RSFQ power enables compact systems with greatly increased computational capability for future government needs, but with no increase in overall power requirements beyond today’s high-end systems. 03
State of the Industry Today, expertise in digital SC technology resides in only a handful of companies and institutes. The U.S. base is shrinking: TABLE E-3. DIGITAL RSFQ TECHNOLOGY’S CURRENT STATE OF THE INDUSTRY Country Entity ISTEC/SRL HYPRES Northrop Grumman Status – Joint government/industry center, probably doing the most advanced work in digital RSFQ anywhere in the world today. – Responsible for the Earth Simulator system. – Private company focused entirely on SC digital electronics. – Has operated the only full-service commercial foundry in the U.S. since 1983. – Had the most advanced foundry and associated design capability until suspended last year. – Still has a strong cadre of experts in the field. Stony Brook U, UC Berkeley, JPL – Currently conducting academic research. Chalmers U of Technology – Currently conducting academic research. NSA, NIST – Have resident expertise. ROADMAP CREATED This report presents a detailed RSFQ technology roadmap, defining the tools and components essential to support RSFQ-based high-end computing by 2010. The end point of this roadmap includes: ■ ■ An RSFQ processor of approximately 1-million gate complexity, operating at a 50 GHz clock rate. A design capability: – consisting of an RSFQ cell library and a complete suite of computer-aided design (CAD) tools. – allowing a competent ASIC digital designer with no background in superconductor electronics to design high-performance processor units. ■ An RSFQ chip manufacturing facility with an established stable process operating at high yields. 04
Page 1 and 2: SUPERCONDUCTING TECHNOLOGY ASSESSME
Page 3 and 4: Summary of Findings The STA conclud
Page 5 and 6: CHAPTER 02: ARCHITECTURAL CONSIDERA
Page 7 and 8: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: CRYOGENIC ENVIRONMENT High-speed ne
Page 29 and 30: ■ ■ Chalmers University in Swed
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: The major issue to be addressed wil
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: TABLE 3.1-1. PUBLISHED SUPERCONDUCT
Page 60 and 61: S G G Chip-side microstrip S Carrie
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
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ELEMENT 2006 2007 2008 2009 2010 Pi
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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TABLE 5-1. I/O TECHNOLOGIES FOR PET
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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