Superconducting Technology Assessment - nitrd

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1,000 Wirebond Lead Inductance (pH) 100 10 TRW Bonded Interconnect Pin (BIP) UNIAX Solder Bump (Flip-Chip) Multilayer TAB Single Metal Layer TAB HTMT Requirement 1 .1 1 10 100 1000 Bond Length or Height (mils) Figure 3. Lead inductance vs. bond length or height for different attach techniques. Use of RSFQ logic circuits offers the advantage of ultra-low power, but the signal levels are low, so chip-to-chip bandwidth is limited unless on-chip driver circuits are used to boost the signal level. Such off-chip drivers need to match the impedance of the driver circuits and the transmission line interconnects. To date, 10 Gbps asynchronous off-chip drivers have been demonstrated. Alternatively, simple synchronous latches may be used. With the planned reduction in feature size and increase in J c to 20 kA/cm 2 , it is not difficult to envision that SCE chips may communicate across an MCM at 50 Gbps in the timeframe required. Further work must be done to address the area and power overhead of these driver circuits. Direct SFQ-to-SFQ signal transmission, which would greatly simplify chip floor planning and signal routing needs development 2) MCM-to-PCB Connection: Three methods of high data rate motherboard-daughterboard connections have already been developed: ■ ■ ■ A connector developed for the IBM superconductor computer project. Another connector developed by IBM for commercial applications using a dendritic interposer technology. A “beam-on-pad” approach developed by Siemens. Although these three techniques are not immediately applicable due to either low interconnect density or low bandwidth, they serve as conceptual springboards for new designs. The main issue with the PCB to MCM interface is that approximately >500 Multi-Gbps lines must connect in the cross-sectional area of 50 mm 2 , or 0.1 mm 2 per pin. For reference, a typical commercial “high-density,” low-speed connector has pins spaced on a 1.25 mm pitch for a density of 1.5 mm 2 per pin; a factor of 15 too large. 3) MCM-to-MCM Connection: The method of routing is to use short flexible ribbon cables, similar to those being used for the I/O cables. The density requirement of 2,000 per edge is considerably less than either for the external I/O cables or for the MCM-to-PCB. Given the length along the MCM bottom and top edges of 20 cm, the signal line pitch would be 4 mils, a density that is available today from flex circuit vendors. 229
While using short flex cables is the leading candidate technology to connect vertically adjacent MCMs, a second method of making these connections based on interposer technology was developed for another SCE program. This design has several advantages: ■ ■ Direct board-to-board communication without the use of a cable. The ability to “make and break” the connections many times. This last aspect greatly increases the ability to assemble and repair the system. 3D Packaging Conventional electronic circuits are designed and fabricated with a planar, monolithic approach in mind where there is only one major active device layer along the z-axis. Any other active layers in the third dimension are placed far away from the layers below and there are none (or only a few) connection between layers. The trend of placing more active devices per unit volume resulted in technologies referred to as 3D packaging, stacking, 3D integration. Compact packaging technologies can bring active devices closer to each other allowing short TOF, which is critical for systems with higher clock speeds. In systems with superconducting components, 3D packaging enables: ■ ■ ■ Higher active component density per unit area. Smaller vacuum enclosures. Shorter distances between different sections of the system. For example, 3D packaging will allow packing terabytes to petabytes of secondary memory in few cubic feet (as opposed to several hundred cubic feet) and much closer to the processor. 3D packaging was initiated in the late 70’s as an effort to improve the packaging densities, lower system weight and volumes and improve electrical performance. Main application areas for 3D packaging are systems where volume and mass are critical 2 . 3 Historically, focal-plane arrays with on-board processing and solid-state data recorder applications for military and commercial satellites have driven the development of 3D packages for memories. For example, data storage unit of the Hubble Telescope consists of 3D stacked memory chips. Recently, 3D packaging has appeared in portable equipment for size savings. These applications have combined memory chips with controller or used few layers of stacked memory chips indicating that the cost of limited number of stacked layers is reduced to be acceptable to mainstream commercial applications. 3D packaging has expanded from stacking homogenous bare die (e.g., SRAM, Flash, DRAM) to stacking heterogeneous bare die and packaged die for “system-in-stack” approaches. Two major types of stacking approaches are homogeneous and heterogeneous stacks. The first approach uses bare die as the layer of the stack for homogeneous stacking (meaning that each layer contains identical die). The I/O pads of the die are rerouted to the edge, and several die are laminated together to form the stack. The edge is lapped to expose the rerouted pads, and metalization is applied on one or more sides to interconnect layers and the cap substrate by connecting exposed pads. The intersection of the layer traces and the bus traces form the “T-Connects,” which are essential for high reliability. Unlike wrap-around or “L-Connect” approaches where step coverage problems can result in a reduced metal cross section, the trace thickness of T-Connects remains the full deposited thickness and contacts the entire cross-section of the exposed pad. 2 S. Al-Sarawi, D. Abbott, P. Franzon, IEEE Trans. Components, Packaging and Manufacturing <strong>Technology</strong>-Part B, 21(1) (1998) p. 1 3 V. Ozguz, J. Carson, in SPIE Optoelectronic Critical Review on Heterogeneous Integration, edited by E. Towe, (SPIE Press, 2000), p. 225. 230
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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CRYOGENIC ENVIRONMENT High-speed ne
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■ ■ Chalmers University in Swed
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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The major issue to be addressed wil
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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TABLE 3.1-1. PUBLISHED SUPERCONDUCT
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S G G Chip-side microstrip S Carrie
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
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ELEMENT 2006 2007 2008 2009 2010 Pi
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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TABLE 5-1. I/O TECHNOLOGIES FOR PET
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
Page 191 and 192: SMT MRAM Another direct selection s
Page 193 and 194: Speed and Density The first planned
Page 195 and 196: 120 0.10 100 Write I (mA) 0.08 0.06
Page 197 and 198: Appendix I
Page 199 and 200: Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Table 5 Reactive Ion Etch Parameter
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: shorts in the first wiring layer we
Page 209 and 210: B. Yield Yield measurements are an
Page 211 and 212: RSFQ logic will eventually find wid
Page 213 and 214: [47] B. Bumble, H. G. LeDuc, J. A.
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Page 217 and 218: Fig. 2. The Schematic View describe
Page 219 and 220: Fig. 4. The VHDL View captures the
Page 221 and 222: Fig. 6. LMeter is specialized softw
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Page 225 and 226: Appendix K
Page 227 and 228: 1. CURRENT STATUS OF OPTICAL INTERC
Page 229 and 230: 1.2. CURRENT OPTICAL INTERCONNECT R
Page 231 and 232: If technology, power, or cost limit
Page 233 and 234: 3.4 COARSE VS. DENSE WAVE DIVISION
Page 235 and 236: 3.5 DEVELOPMENTS FOR LOW TEMPERATUR
Page 237 and 238: 5. ROADMAP The roadmap below shows
Page 239 and 240: Appendix L
Page 241: The bandwidth, chip density and int
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Page 247 and 248: Intermediate Temperature stage Disp
Page 249 and 250: Small Cryocoolers Among commercial
Page 251 and 252: Although cooling of the 4 K circuit
Page 253 and 254: Supplying DC current to all of the
Page 255 and 256: These properties enable the possibi
Page 257: For additional copies, please conta
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