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Superconducting Technology Assessment - nitrd

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CAD<br />

PRESENT CAD CAPABILITY<br />

The integrated circuit design software developed by Stony Brook University and the University of Rochester was<br />

integrated into a single software suite at Northrop Grumman. The readiness of U.S.-based design methodology and<br />

CAD tools will be described in detail using the Northrop Grumman capability as an example. While built upon the<br />

academic projects, it also leverages the methodology and software that serves the commercial semiconductor ASIC<br />

world. Where possible, semiconductor standards were adhered to.<br />

Circuit Design<br />

VHDL<br />

Schematic<br />

LVS<br />

DRC<br />

Layout<br />

RSFQ Gate Library<br />

Gate<br />

Pcells<br />

Lmeter<br />

Schematic<br />

Malt<br />

WRSpice<br />

Symbol<br />

VHDL<br />

Structure<br />

Layout<br />

Netlist<br />

VHDL<br />

Generic<br />

Fig. 1. Circuit design and verification, top, is distinct from logic gate library development, bottom. The chip foundry publishes the gate library<br />

to serve all users. Customers construct complex circuits from the gates, to satisfy their unique performance goals.<br />

In the following description we will repeatedly distinguish between the gate library developer and the circuit<br />

designer. Division of labor between these two roles, illustrated in Figure 1, is among the most important steps in<br />

design methodology. The role of the circuit designer is to architect, simulate and verify complex designs. This can<br />

be accomplished without knowledge of all of the details of the device physics, foundry process, or CAD software.<br />

As in the commercial ASIC world, device and gate libraries are published by the foundry. These include, at<br />

minimum, device models for physical-level simulation and parameterized-cell (Pcell) physical layout of devices and<br />

gates. Commercial foundries emphasize formal verification of designs submitted for fabrication. Therefore, the<br />

foundry typically provides CAD-based design verification rules for design rule checking (DRC) and layout-versusschematic<br />

(LVS). Some commercial foundries require clean DRC and LVS verification run files to be submitted with<br />

the design prior to fabrication. The foundry may also perform additional verification checks and require design<br />

modifications to physical layout before tooling.<br />

203

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