Superconducting Technology Assessment - nitrd

Potential Problems
The initial version of the proposal does not adequately address microarchitectural and other important design issues
(e.g., memory latency tolerance), which underscores both the lack of expertise in real world processor and system
design and the limitations of the bottom-up approach used in the Japanese RSFQ design project. Nevertheless, it
is reasonable to believe that significant revisions will be made to the initial version of the proposal to address these
as well as the other issues before and after the expected start of the project in 2005.
2.3 MICROPROCESSORS – READINESS
Progress Made
Recent progress in RSFQ processor logic and memory design has created a foundation on which to build the next
step towards full-fledged RSFQ processors with a clock frequency of 50 GHz. Table 2-4 shows the readiness of key
components and techniques to be used at superconductor processor and system design levels.
TABLE 2-4. READINESS OF SUPERCONDUCTOR PROCESSOR ARCHITECTURE AND DESIGN TECHNIQUES
Design Level
Readiness
Basis
Comments
Data processing
Component validation
HYPRES, NGST-Stony Brook Univ,
Integer data processing chips;
modules: clocking,
in relevant environment
SRL-ISTEC (Japan)
the logical design of the 32-bit
structure, and design
FLUX-2 floating-point multiplier
On-chip processor
Component validation
NGST-Stony Brook Univ,
Vector registers; small-size register
storage structures:
in laboratory environment
SRL-ISTEC
files and small memory in CORE1
organization, capacity,
and FLUX-1 chips
and bandwidth
Single-chip microprocessors:
Component validation
SRL-ISTEC,
8-bit FLUX-1 and CORE1 processor
microarchitecture and
in laboratory environment
NGST-Stony Brook Univ
prototype chips; a partitioned, FLUX-1
physical design
bit-streaming microarchitecture
Chipsets: microarchitecture,
Experimental demonstration
NGST-Stony Brook Univ
60 Gb/link/sec chip-to-chip data
partitioning, physical design,
of critical functions in
transfer over a MCM, clock
and chip-to-chip communica-
laboratory environment
resynchronization with FIFOs
tion and synchronization
Off-chip memory:
Analytical and experimental
NEC, HYPRES,
2-4 kbit SFQ, and 64 kbit
organization, capacity, latency,
demonstration of critical
UC Berkeley
hybrid SFQ-CMOS single-bank,
and data bandwidth
functions
non-pipelined memory chips
Latency-tolerant
Analytical
HTMT petaflops compute feasibility
Architectural techniques
architectures for
and simulation studies
study, the Japanese 2004 proposal
studied/proposed: multithreading,
superconductor
for a petaflops system
prefetching, thread migration and
processors and systems
vector processing
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