Superconducting Technology Assessment - nitrd

In summary, several ideas have been studied. In two of these, the memory cells were the NEC vortex transitional
(VT) type cells, which were developed for use with voltage-state logic and require voltage-state drivers. One design
provided for SFQ input and output pulses on a 256-bit array with potential for high speed. However, scaled to
64 kb, this array would have untenable power dissipation and large size. The other group did not demonstrate a
complete system.
The cryo-RAM (CRAM) developed at HYPRES had attractive estimated access and cycle times for 4-kb blocks, but
no high-speed data. The estimates for power and access and cycle times scaled to 64-kb are attractive. Circuit
density and cycle and access times would be more favorable with increased current density. The ballistic RAM
(BRAM) is an interesting concept that will require more research. For all, more advanced fabrication would lead
to greater circuit density.
SFQ RAM Readiness for Investment
Although SFQ RAM technology is not as advanced as hybrid CMOS, the panel feels that very attractive concepts
exist and should be investigated to support RSFQ processors for HEC. An effort should be made to further evaluate
the CRAM and BRAM in order to project their advantages and disadvantages and to quantify power, access time,
density, and probability of success. The panel urges that the better choice be pursued at least to the bit-slice stage
to further define the key parameters. If successful, the development should be completed.
SFQ RAM Projections
The CRAM design should be scaled to a 20 kA/cm 2 process and 64-kb RAM to determine the important parameters
of speed, power, and chip size. The BRAM concept will require more design evaluation to determine its potential,
but either of these ideas could have advantages over the hybrid Josephson-CMOS memory in speed and power.
As noted for the hybrid memory, memory chip design will require close collaboration between the architecture and
memory teams in order to find the best processor-memory communication and internal memory chip organization
to meet the read/write latency, access cycle time, and bandwidth requirements of 50 GHz processors.
SFQ RAM Issues and Concerns
As in any large RSFQ circuit, margins and flux trapping may be problems. The testing of the CRAM was only done
at low speed, so new issues may arise when operated at high speed. In the present DRO BRAM concept, methods
for refreshing will have to be explored in order to retain the beneficial aspects of this memory.
SFQ RAM Roadmap
TABLE 3.2-5 SFQ RAM ROADMAP AND INVESTMENT PLAN
Milestone Year Cost ($M)
Design 64-kb CRAM and BRAM and design bit slice for test
and evaluation
Test and evaluate bit slice
Design, test, and evaluate complete 64 kb memory
Interface memory with processor
Integrate memory with processor; Test and evaluate
Total Investment
2006
2007
2008
2009
2010
2.45
2.45
2.45
2.45
2.45
12.25
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