Superconducting Technology Assessment - nitrd

Technical Details
Today’s best superconductive integrated circuit processes are capable of producing digital logic IC chips with 10 5
JJ/cm 2 . On-chip clock speeds of 60 GHz for complex digital logic and 770 GHz for a static divider (toggle flip-flop)
have been demonstrated. Large digital IC chips, with JJ counts exceeding 60,000 have been fabricated. IC chip
yield is limited by defect density rather than by parameter spreads. At present, integration levels are limited by
wiring and interconnect density rather than junction size, making the addition of more wiring layers key to the
future development of this technology.
Panel’s Approach
The panel assessed the status of IC chip manufacturing for superconductive RSFQ electronics at the end of calendar
year 2004, projected the capability that could be achieved in the 2010 time-frame, and estimated the investment
required for the development of RSFQ high-end computers within approximately five years.
Costs
Manufacturing RSFQ IC chips of the required complexity and in the required volumes for petaflops-scale computing
will require both recurring costs associated with operation of the fabrication facility, and nonrecurring costs mainly
associated with the procurement cost of the fabrication tools and one-time facilities upgrades.
Roadmap Criteria
The roadmap to an SCE IC chip manufacturing capability was constructed to meet the following criteria:
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Earliest possible availability of IC chips for micro-architecture, CAD, and circuit design development efforts.
These IC chips must be fabricated in a process sufficiently advanced to have reliable legacy to the final
manufacturing process.
Firm demonstration of yield and manufacturing technology that can support the volume and cost
targets for delivery of known good die for all superconductive IC chip types comprising a petascale system.
Support for delivery of ancillary superconductive thin film technologies such as flip-chip, single-chip,
and multi-chip carriers and MCM and board-level packaging for technology demonstrations.
Availability of foundry services to the superconductive R&D community and ultimately for other
commercial applications in telecommunications, instrumentations, and other applications.
Interconnects and System Input/Output
Packaging and chip-to-chip interconnect technology should be reasonably
in hand.
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Wideband data communication from low to room temperature is a challenge
that must be addressed.
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Total investment over five-year period: $92 million.
Essential supporting technologies for packaging, system integration, and wideband communications—particularly
wideband data output from the cryogenic to ambient environment— were assessed.
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