Superconducting Technology Assessment - nitrd

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APPENDIX A: TERMS OF REFERENCE 135 APPENDIX B: PANEL MEMBERS 139 APPENDIX C: GLOSSARY 143 APPENDIX D: INTRODUCTION TO SUPERCONDUCTOR 147 SINGLE FLUX QUANTUM CIRCUITRY (The appendices below can be found on the attached CD but are not printed in this report.) APPENDIX E: SOME APPLICATIONS FOR RSFQ 155 APPENDIX F: SYSTEM ARCHITECTURES 161 APPENDIX G: ISSUES AFFECTING RSFQ CIRCUITS 169 APPENDIX H: MRAM TECHNOLOGY FOR RSFQ HIGH-END COMPUTING 177 APPENDIX I: SUPERCONDUCTOR INTEGRATED CIRCUIT 185 FABRICATION TECHNOLOGY APPENDIX J: CAD 203 APPENDIX K: DATA SIGNAL TRANSMISSION 213 APPENDIX L: MULTI-CHIP MODULES AND BOARDS 227
INDEX OF FIGURES CHAPTER 01: INTRODUCTION 1-1 2004 ITRS update shows RSFQ as the lowest risk potential emerging technology 09 for processing beyond silicon 1-2 Roadmap for RSFQ technology tools and components 12 1-3 Conceptual architecture 14 CHAPTER 02: ARCHITECTURAL CONSIDERATIONS FOR SUPERCONDUCTOR RSFQ MICROPROCESSORS 2-1 8-processor node of the proposed Japanese superconductor petaflops system 31 2-2 50-GHz multi-chip processor microprocessor design roadmap 37 CHAPTER 03: SUPERCONDUCTIVE RSFQ PROCESSOR AND MEMORY TECHNOLOGY 3.1-1 Roadmap and major milestones for RSFQ processors 43 3.1-2 Photograph of 1-cm 2 Flux-1 63K JJ microprocessor chip 44 3.1-3 Signal and ground pad geometry used on Flux-1 47 3.2-1 Hybrid Josephson-CMOS RAM operates at 4 K 54 3.2-2 Wafer with embedded CMOS memory chips for direct wiring of Josephson peripheral circuits 55 3.2-3 Diagram of FS-TMR cell 61 3.2-4 Cryogenic RAM roadmap 66 3.3-1 ADC chip containing about 6,000 JJs 68 3.3-2 A bit-serial superconductor microprocessor featuring 6,300 JJs, 7 instructions, and a 16 GHz clock 68 CHAPTER 04: SUPERCONDUCTIVE CHIP MANUFACTURE 4-1 Schematic diagram of functions included in IC chip manufacture 78 4-2 Fabrication of RSFQ ICs is accomplished using semiconductor equipment and processes 79 4-3 Demonstrations of RSFQ circuit speed with increasing Jc 80 4-4 Notional cross-section of the superconductive IC chip fabrication process illustrating salient 85 features of an advanced process which includes four interconnect levels, planarization, and plugs 4-5 Projections of RSFQ circuit speeds with increasing Jc 87 4-6 Timeline for development of SCE manufacturing capability 92
Page 1 and 2: SUPERCONDUCTING TECHNOLOGY ASSESSME
Page 3 and 4: Summary of Findings The STA conclud
Page 5 and 6: CHAPTER 02: ARCHITECTURAL CONSIDERA
Page 7: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27 and 28: CRYOGENIC ENVIRONMENT High-speed ne
Page 29 and 30: ■ ■ Chalmers University in Swed
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: The major issue to be addressed wil
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
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TABLE 3.1-1. PUBLISHED SUPERCONDUCT
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S G G Chip-side microstrip S Carrie
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
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ELEMENT 2006 2007 2008 2009 2010 Pi
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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TABLE 5-1. I/O TECHNOLOGIES FOR PET
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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