Superconducting Technology Assessment - nitrd

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TABLE 1. COMPONENT TECHNOLOGY DEVELOPMENT SUMMARY DEVICE CURRENT STATUS 2005 DESIRED STATE 2010 CRYOGENIC USE TESTED ONGOING R&D VCSEL Based CWDM Interconnect Systems: 12x4λ @ 300K DARPA Terabus 12 x 4λ x 10 Gbps 8x8λ x 50 Gbps N Y LIGHT SOURCES 50 Gbps VCSEL Arrays 10 Gbps 50 Gbps Y Y Frequency Comb Lasers 32λ x 1550 nm 64λ x 980 nm N/A N OPTICAL MODULATORS VCSEL used as DWDM modulator 2.5 Gbps 50 Gbps N Y Low Voltage Amplitude Modulator @ 40 K 4-6 volts On-Off/ 40 Gbps Single Devices/ COTS 0.5 volt on-off/ 50 Gbps Arrays N Y Exotic Modulator Materials: Organic Glass/Polymer/Magneto-Optic Materials studies show 3x improvement over conventional materials 6-10 fold improvement in devices N Y OPTICAL RECEIVERS Amplifierless Receivers matched to superconductors 20 Gbps demonstrated 50 Gbps Array N N 25/50 Gbps Receiver Arrays @ 300K 50 Gbps Single Devices – COTS 4 x 40 Gbps arrays Lab Ideally, word-wide arrays N/A N ELECTRONIC DEVICES Low Power, 50 Gbps Amplifier/Driver Arrays @ 40 K Single Amplifiers (InP-HEMT) – COTS Lower power, ideally, word-wide arrays Y N PASSIVE COMPONENTS Cryogenic Electrical Ribbon Cables at 25/50 Gbps 3 Gbps 25/50 Gbps Y N Optical Ribbon Cables @ 4 K, 40 K COTS meet Commercial Specs/ Fibers OK at 4 K Cables at 4 K N N Optical WDM Components @ 4 K, 40 K COTS meet Commercial Specs 4 K Operation N N 223
5. ROADMAP The roadmap below shows the specification and the proposed schedule of the critical project stages related to the development of the interconnect technology from cryogenic processors to room temperature mass memory systems for a system demonstration. The roadmap assumes full-government funding. There are no known industrial companies in the U.S. that would fully support this work at this stage. DATA SIGNAL TRANSMISSION TECHNOLOGY DEVELOPMENT ROADMAP Existing Funding Not funded FISCAL YEARS VCSEL Based CWDM Interconnects Systems: 12 x 4 l @ 300K DARPA TERABUS LIGHT SOURCES 50 Gbps VCSEL Arrays 2006 2007 2008 2009 2010 1H 2H 1H 2H 1H 2H 1H 2H 1H 2H 10 Gbps System Demo 4 x 40 Gbps, 300k 64 x 50 Gbps, 40k Frequency Comb Lasers OPTICAL MODULATORS VCSEL array used as DWDM modulator 64 DWDM @ 980nm 10 Gbps 25 Gbps 50 Gbps @ 40k Low Voltage Amplitude Modulator Arrays @ 40K Single 10 Gbps Single 40 Gbps@300k 50 Gbps Array Exotic Modulator Materials: Organic Glass/Polymer/Magneto-Optic OPTICAL RECEIVERS Complete Material Studies Improved Materials Prototype Devices Single Devices @ 40k w/Goal Material Device Array @ 40k Amplifierless Receiver Arrays matched to superconductors 4 x 40 Gbs InGaAs Array @ 300k 4 x 40 Gbps Array to SC @ 4k 64 x 50 Gbps Array to SC @ 4k 25/50 Gbps Receiver Arrays @ 300K ELECTRONIC DEVICES Low Power, 50 Gbps Amplifier/Driver Arrays@ 40K 64 x 50 Gbps Array 64 x 50 Gbps Array PASSIVE COMPONENTS Cryogenic Electrical Ribbon Cables at 25/50 Gbps Optical Ribbon Cables @ 4K, 40K 128 x 25 Gbps 64 x 50 Gbps Optical WDM Components @ 4K, 40K Test Cable & Connectors @ 4, 40k Test @ 4, 40k Cryogemic Componets Development Done Cryogemic Componets Development Done 224
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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CRYOGENIC ENVIRONMENT High-speed ne
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■ ■ Chalmers University in Swed
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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The major issue to be addressed wil
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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TABLE 3.1-1. PUBLISHED SUPERCONDUCT
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S G G Chip-side microstrip S Carrie
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
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ELEMENT 2006 2007 2008 2009 2010 Pi
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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TABLE 5-1. I/O TECHNOLOGIES FOR PET
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
Page 185 and 186: Bias Currents A major cause of degr
Page 187 and 188: Power and bias current Power is dis
Page 189 and 190: Appendix H
Page 191 and 192: SMT MRAM Another direct selection s
Page 193 and 194: Speed and Density The first planned
Page 195 and 196: 120 0.10 100 Write I (mA) 0.08 0.06
Page 197 and 198: Appendix I
Page 199 and 200: Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Table 5 Reactive Ion Etch Parameter
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: shorts in the first wiring layer we
Page 209 and 210: B. Yield Yield measurements are an
Page 211 and 212: RSFQ logic will eventually find wid
Page 213 and 214: [47] B. Bumble, H. G. LeDuc, J. A.
Page 215 and 216: Appendix J
Page 217 and 218: Fig. 2. The Schematic View describe
Page 219 and 220: Fig. 4. The VHDL View captures the
Page 221 and 222: Fig. 6. LMeter is specialized softw
Page 223 and 224: Fig. 8. Layout-versus-Schematic ver
Page 225 and 226: Appendix K
Page 227 and 228: 1. CURRENT STATUS OF OPTICAL INTERC
Page 229 and 230: 1.2. CURRENT OPTICAL INTERCONNECT R
Page 231 and 232: If technology, power, or cost limit
Page 233 and 234: 3.4 COARSE VS. DENSE WAVE DIVISION
Page 235: 3.5 DEVELOPMENTS FOR LOW TEMPERATUR
Page 239 and 240: Appendix L
Page 241 and 242: The bandwidth, chip density and int
Page 243 and 244: While using short flex cables is th
Page 245 and 246: We must note that the reparability
Page 247 and 248: Intermediate Temperature stage Disp
Page 249 and 250: Small Cryocoolers Among commercial
Page 251 and 252: Although cooling of the 4 K circuit
Page 253 and 254: Supplying DC current to all of the
Page 255 and 256: These properties enable the possibi
Page 257: For additional copies, please conta
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