Superconducting Technology Assessment - nitrd

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1.6.2 FAST, LOW LATENCY MEMORY Large and fast systems will require fast memory that can be accessed in a small number of machine cycles. As the cycle time decreases, this requirement becomes very demanding, limited by the speed of light as well as the memory speed itself, and presently there is no memory technology that can provide the combination of access time and size that will be needed. The panel has identified three promising approaches to placing significant amounts of fast, low latency RAM at 4 K next to the processor: ■ ■ ■ Hybrid JJ-CMOS RAM. SFQ RAM. Monolithic RSFQ-MRAM. In addition, CMOS DRAM and MRAM could be located at an intermediate cryogenic temperature (40 - 77 K) to reduce latency. The system architect will then have several options in designing the memory hierarchy. 1.6.3 HIGH SPEED INPUT/OUTPUT Communicating high-bandwidth data up from the cryogenic environment to room temperature is also a challenge because present drive circuits consume more power than can be tolerated at the low-temperature stage. One approach is to communicate electrically up to an intermediate temperature stage and then optically up to room temperature. 1.6.4 CAD TOOLS CAD tools and circuit building blocks must be in place so that designs can be done by a competent digital designer who is not a superconductivity expert. These can build on the tools for CMOS circuitry. 1.6.5 REFRIGERATION Refrigeration is not considered to be a problem. Existing coolers currently used for applications such as superconducting magnets and nuclear accelerators will meet the need. 1.7 STATE OF THE INDUSTRY Today, expertise in digital superconducting technology resides in only a handful of companies and institutes: ■ ■ ■ The Japanese ISTEC (International Superconductivity Technology Center) SRL (Superconducting Research Laboratory) is a joint government/industry center that probably has the most advanced work in digital RSFQ anywhere in the world today. HYPRES, a small company in Elmsford, NY, is focused entirely on superconducting digital electronics. Its current market is primarily DoD Radio Frequency (RF) applications and related commercial communication systems. It has operated the only full-service commercial foundry in the U.S. since 1983. Northrop Grumman (Space Technology) had the most advanced foundry and design capability until it was suspended last year. That division still has a strong cadre of experts in the field, and the company has a continuing research effort in Baltimore, Maryland. 15
■ ■ Chalmers University in Sweden is developing RSFQ technology to reduce error rates in CDMA cell phone base stations. Academic research continues at the Jet Propulsion Laboratory and the Universities of California, Berkeley and Stony Brook. Among government agencies, NIST (Boulder), NSA, and ONR have resident expertise. Some additional companies are working in analog or power applications of superconductivity, but they are not involved in digital devices. 1.8 CONTENTS OF STUDY The panel organized its deliberations, findings, and conclusions into five topical areas, with each chapter going into detail on one of the following: ■ ■ ■ ■ ■ Architectural considerations. Processors and memory. Superconductor chip manufacturing. Interconnect and input/output. System integration. (The attached CD contains the full text of the entire report and all appendices.) 1.9 CHAPTER SUMMARIES Architectural Considerations No radical execution paradigm shift is required for superconductor processors, but several architectural and design challenges need to be addressed. ————— By 2010 architectural solutions for 50-100 GHz superconductor processors with local memory should be available. ————— Total investment over five-year period: $20 million. RSFQ logic at high clock rates introduces unique architectural challenges. Specifically: ■ ■ ■ The on-chip, gate-to-gate communication delays in 50 GHz microprocessors will limit the chip area reachable in one cycle to less than 2 mm. One can no longer employ clock or data buses. Local clocks will have to be resynchronized both on-chip and between chips. 16
Page 1 and 2: SUPERCONDUCTING TECHNOLOGY ASSESSME
Page 3 and 4: Summary of Findings The STA conclud
Page 5 and 6: CHAPTER 02: ARCHITECTURAL CONSIDERA
Page 7 and 8: CHAPTER 06: SYSTEM INTEGRATION 6.1
Page 9 and 10: INDEX OF FIGURES CHAPTER 01: INTROD
Page 11 and 12: APPENDIX G: ISSUES AFFECTING RSFQ C
Page 13 and 14: CONTENTS OF CD EXECUTIVE SUMMARY CH
Page 15 and 16: LIMITATIONS OF CURRENT TECHNOLOGY C
Page 17 and 18: State of the Industry Today, expert
Page 19 and 20: 01 This document presents the resul
Page 21 and 22: 1.2 LIMITATIONS OF CONVENTIONAL TEC
Page 23 and 24: 1.3.2 RSFQ ATTRIBUTES Important att
Page 25 and 26: The end point of this roadmap defin
Page 27: CRYOGENIC ENVIRONMENT High-speed ne
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: The major issue to be addressed wil
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
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Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: TABLE 3.1-1. PUBLISHED SUPERCONDUCT
Page 60 and 61: S G G Chip-side microstrip S Carrie
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
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ELEMENT 2006 2007 2008 2009 2010 Pi
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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TABLE 5-1. I/O TECHNOLOGIES FOR PET
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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