Superconducting Technology Assessment - nitrd

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MRAM Major Issues and Concerns Materials Data A major concern is the paucity of low-temperature experimental data. Data needs to be acquired early on the fundamental properties of candidate magnetic materials and their performance in a memory element. Extrapolations from 300 K to 4 K appear promising for FS-TMR MRAM but are not assured. SMT memory may be more compatible in device resistance and switching speed with RSFQ logic than FS devices, but it is even more embryonic. It should be emphasized, however, that the opportunity afforded by combining MRAM with RSFQ circuits will remain unexplored unless this ultra-high performance computing niche is funded by government investment. Collaborators Another issue is establishing collaboration with a suitable organization for device fabrication, and, ultimately, memory product chips. For superconducting-MRAM development, all Cu wiring needs to be replaced by Nb. Compatibility needs to be addressed and process flow determined. For monolithic RSFQ-MRAM, both MRAM and RSFQ fabrication processes will need to be combined, and process compatibility will be more complex. The major organizations and their activities are noted below: ■ ■ ■ ■ ■ DARPA accelerated MRAM device development at IBM, Motorola, and NVE Corporation through seed investment in the 90’s. Since then, Motorola’s Semiconductor Sector (now Freescale Semiconductor) has invested several hundred million dollars to build and operate an MRAM fabrication line currently producing 4Mbit chips. Freescale is also collaborating with Honeywell to build MRAM radiation-hardened devices. IBM may be another potential partner, although the company has maintained a lower level R&D effort to date ($8-10 M/year) without any commitment to production. NVE Corporation continues some level of activity in spintronics. Flux Trapping Flux trapping, which has been identified as a generic issue for RSFQ circuits, is of special concern here since MRAM incorporates ferromagnetic films in the chip. The effects should be evaluated and methods developed to avoid this problem. 65
3.2.4 MEMORY – SUMMATION The roadmap and Investment plan for cryogenic RAM envisions initiating development of the three RAM options discussed above. Each technology would be monitored and evaluated for progress and possible show stoppers. Approximately halfway through the five-year cycle, the efforts and investment allocation would be critically reviewed. The expected relative merits of each technology as the panel understands them are given in Table 3.2-1. These would be updated periodically during the time of the roadmap. Hybrid JJ-CMOS 64-kb bit-slice 256-kb RAM 128-kb RAM SFQ RAM 64-kb bit-slice 64-kb RAM 128-kb RAM MRAM Collaborators Test/Compare FS/SMT 32-kb RAM 128-kb RAM Cryo-RAM Decisions on Resources 128-kb RAM 2006 2007 2008 2009 2010 Figure 3.2-4. Cryogenic RAM roadmap. Memory Investment Summary TABLE 3.2-10. INVESTMENT PLAN FOR CRYOGENIC RAM (in $M) Memory <strong>Technology</strong> JJ-CMOS RAM SFQ RAM JJ-MRAM Memory Total Investment $14.2 $12.5 $22 $48.45 66
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
Page 27 and 28: CRYOGENIC ENVIRONMENT High-speed ne
Page 29 and 30: ■ ■ Chalmers University in Swed
Page 31 and 32: Random Access Memory Options Random
Page 33 and 34: Compact Package Feasible Thousands
Page 35 and 36: The major issue to be addressed wil
Page 37 and 38: 02 No radical execution paradigm sh
Page 39 and 40: The key challenges at the processor
Page 41 and 42: 2.2 MICROPROCESSORS - CURRENT STATU
Page 43 and 44: 2.2.3 CORE1 BIT-SERIAL MICROPROCESS
Page 45 and 46: Potential Problems The initial vers
Page 47 and 48: The microarchitecture of supercondu
Page 49 and 50: 2.5 MICROPROCESSORS - CONCLUSIONS A
Page 51: 2.7 MICROPROCESSORS - FUNDING In th
Page 54 and 55: SUPERCONDUCTIVE RSFQ PROCESSOR AND
Page 56 and 57: 3.1 RSFQ PROCESSORS The panel devel
Page 58 and 59: TABLE 3.1-1. PUBLISHED SUPERCONDUCT
Page 60 and 61: S G G Chip-side microstrip S Carrie
Page 62 and 63: 3.1.3 RSFQ PROCESSORS - ROADMAP The
Page 64 and 65: 3.1.5 RSFQ PROCESSORS - ISSUES AND
Page 66 and 67: Since these memory concepts are so
Page 68 and 69: Simulations show that the input int
Page 70 and 71: SFQ RAM Status The results of five
Page 72 and 73: Investment for SFQ Memory The inves
Page 74 and 75: 4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
Page 76 and 77: The roadmap identifies early analyt
Page 80 and 81: 3.3 CAD TOOLS AND DESIGN METHODOLOG
Page 82 and 83: Issues and Concerns Present simulat
Page 84 and 85: Investment The investment estimated
Page 87 and 88: 04 By 2010 production capability fo
Page 89 and 90: Table 4-1 summarizes the roadmap fo
Page 91 and 92: 4.1 SCE IC CHIP MANUFACTURING - SCO
Page 93 and 94: Significant activity in the area of
Page 95 and 96: 4.3 SCE CHIP FABRICATION FOR HEC -
Page 97 and 98: The superconductive IC chip fabrica
Page 99 and 100: Table 4-6 shows how gate speed depe
Page 101 and 102: Parameter spreads in superconductiv
Page 103 and 104: TABLE 4-9. SCALING REQUIREMENTS FOR
Page 105 and 106: ELEMENT 2006 2007 2008 2009 2010 Pi
Page 107 and 108: A potential savings of ~40% in the
Page 109 and 110: 05 Packaging and chip-to-chip inter
Page 111 and 112: TABLE 5-1. I/O TECHNOLOGIES FOR PET
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Appendix H
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SMT MRAM Another direct selection s
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Speed and Density The first planned
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120 0.10 100 Write I (mA) 0.08 0.06
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Appendix I
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Table 1 Representative Nb and NbN-B
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ground plane may be located either
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Table 5 Reactive Ion Etch Parameter
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Table 6 Junction Array Summary of T
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shorts in the first wiring layer we
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B. Yield Yield measurements are an
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RSFQ logic will eventually find wid
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[47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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