Superconducting Technology Assessment - nitrd

Investment for SFQ Memory
The investment plan (Table 3.2-5) for development of SFQ RAM reflects only manpower costs for design and test.
Masks and fabrication costs are in the foundry budgets, the cryogenic high-speed test bench is included in the section
3.1 plan, and RAM-unique test equipment is shared with hybrid JJ-CMOS and MRAM. The total investment for SFQ
RAM is $12.25 million.
3.2.3 MEMORY – MRAM
The panel identified three options for cryogenic MRAM that differ in speed, power, and maturity. RSFQ-MRAM at
4 K could provide the large, low-latency cryogenic RAM required to support RSFQ processors in HEC applications.
TABLE 3.2-6. OPTIONS FOR CRYOGENIC MRAM
Option
Speed
Power
Maturity
RSFQ-MRAM at 4 K
Very High
Very Low
Very Low
SC-MRAM at 4 K
High
Low
Low
MRAM at 40 K
Moderate
Moderate
Medium
Background
MRAM bits are small ferromagnetic stacks that have two stable magnetic states, retain their value without applied
power, and are sensed by coupled resistive elements. MRAM relies on spintronics, where the magnetic polarization
of the films affects the multilayers coupled to the ferromagnets. MRAM combines spintronic devices with CMOS
read/write circuitry to deliver a combination of attributes not found in any other CMOS memory: speed comparable
to SRAM, cell size comparable to or smaller than DRAM, and inherent nonvolatility independent of an operating
temperature or device size. Industry is presently developing room temperature MRAM for high performance,
nonvolatile applications.
The panel evaluated MRAM that use two different spintronic devices:
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Field switched (FS) tunneling magnetoresistive (TMR) devices.
Spin momentum transfer (SMT) giant magnetoresistive (GMR) metallic devices.
Both devices rely on spin-polarization to produce a magnetoresistive ratio (MR) that can be distinguished as
“0” and “1” with low bit error rate (BER).
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