Superconducting Technology Assessment - nitrd

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SFQ logic operates by generating, storing, and transmitting identical SFQ pulses. Data pulses are transmitted by direct connection between adjacent gates. Data is transmitted to distant gates as SFQ pulses through impedancematched passive microstripline or stripline as shown in Figure 4. When an SFQ pulse is fed into the left-most inductor, a clock-wise current i = Φ 0 /L appears in the inductor-JJ pair, which adds to the current in the junction. If the sum of the SFQ current and the bias exceeds I C , the junction switches and the SFQ pulse is transmitted down the line. Figure 5 illustrates three basic SFQ circuit configurations: data latch, OR gate, and AND gate. The two-junction comparator is the basic decision-making element in SFQ logic (Figure 5a). The data latch of Figure 5a includes an input junction (J1), an inductor to store an SFQ pulse (“1”), and a comparator J2/J3 that determines whether or not an SFQ pulse will be transmitted for each clock pulse. An SFQ pulse appearing at J1 will switch J1 and store one flux quantum in the inductor between J1 and J2/J3. The stored flux quantum adds a current ~Φ 0 /L in J3. If there is a flux quantum in the latch when the clock pulse arrives, J3 switches, an SFQ pulse is transmitted, and the latch is reset to 0. If there is no flux quantum in the latch when the clock arrives, the current in J3 is insufficient to switch J3 and no SFQ pulse is transmitted. The OR and AND gates depicted in Figure 5 represent the inputs to the latch. In the OR gate, an SFQ pulse at either input will be transmitted to the output and into a latch. As usual, SFQ pulses have to arrive “simultaneously” at both inputs to transmit an output in Figure 5c. The two inputs would be clocked from preceding latches to ensure simultaneous arrival. Clock Data J2 J1 J3 Figure 5. Representative SFQ gates (a) SFQ data latch (DFF) (b) Or gate (Merger) (c) AND gate The comparator must be robust in order to withstand parameter variations and thermal noise that can speed-up or delay switching. These have the effect of reducing operating margins, which translates into higher incidence of errors. The effective operating margins are those for which an acceptable bit-error-rate (BER) is achieved. This is quantified in terms of the acceptable range of DC current injected between the two junctions. The minimum junction critical current (I C ) is a compromise between thermal noise considerations discussed above and existing lithography limits for junctions and inductors. Since junctions are connected to small inductances, L, and LI C ~2x 10 -15 Wb, the maximum local inductance is ~ 20 pH. An increase in J C must be accompanied by an equivalent reduction in junction area. At 20 kA/cm 2 , the smallest junctions will be ~ 0.8 µm. To achieve a factor of two increase in switching speed, J C should be 80 kA/cm 2 and the smallest junctions would be about 0.4 µm. Lower I C requires larger inductors that occupy more space and reduce gate density. Higher I C increases the effect of parasitics. Bias resistors are used to convert low voltage supplies to fixed current sources for each junction. They are not shown in any of the circuits, but are implied in series with the supply current. Although power dissipation is very low compared with all other technologies, there is continuous power dissipation in the bias resistors (R B ) equal to 0.5I C2 R B , assuming junctions are biased at ~0.7I C . A more convenient measure is 0.7I C V B , since R B is set equal to V B /0.7I C . For 2 mV and 100 µA, the static power dissipation is ~0.14 µW/JJ. Assuming 10 JJs/gate, the static power per gate is ~1.4 µW. 151
Similar to CMOS, the irreducible power dissipation only occurs during SFQ switching events when a voltage appears across the junction. Assuming a junction switches at the frequency f, the minimum power dissipation is P SFQ =I C V=I C Φ 0 f. Based on the present minimum I C ~ 100 µA, P SFQ = 0.2 nW/GHz per junction. Assuming ten JJs per gate and five JJs switch each cycle per gate, P SFQ = 1 nW/GHz per gate. At 100 GHz, P SFQ = 0.1 µW/gate. The ratio of the static power to the switching power is ~20 at 100 GHz. Additional information about JJ technology can be found in numerous books, including: ■ T. Van Duzer and C.W. Turner, Principles of Superconductive Devices and Circuits, (Elsevier, NY, 1981). ■ Alan Kadin, Introduction to Superconducting Circuits (John Wiley and Sons, NY, 1999). Review articles on RSFQ technology include: ■ ■ ■ K.K. Likharev and V.K. Semenov, "RSFQ Logic/Memory Family: A New Josephson Junction Technology for Sub-Terahertz Clock-Frequency Digital Systems," IEEE Transactions on Applied Superconductivity, vol. 1, pp. 2-28, March 1991. K.K. Likharev, "Superconductor Devices for Ultrafast Computing," in Applications of Superconductivity," H. Weinstock, Ed., Dordrecht, Kluwer, 1999. A.H. Silver, A.W. Kleinsasser, G.L. Kerber Q.P. Herr, M. Dorojevets, P. Bunyk, and L. Abelson, "Development of superconductor electronics technology for high-end computing," Superconductor Science and Technology, vol. 16, pp. 1368-1374, December 2003. 152
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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CRYOGENIC ENVIRONMENT High-speed ne
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■ ■ Chalmers University in Swed
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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The major issue to be addressed wil
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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TABLE 3.1-1. PUBLISHED SUPERCONDUCT
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S G G Chip-side microstrip S Carrie
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
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ELEMENT 2006 2007 2008 2009 2010 Pi
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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TABLE 5-1. I/O TECHNOLOGIES FOR PET
Page 113 and 114: For further discussions of the opti
Page 115 and 116: 5.1.3 OPTICAL INTERCONNECT TECHNOLO
Page 117 and 118: In this case, an optical receiver w
Page 119 and 120: Examples of what has been achieved
Page 121 and 122: 5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
Page 123 and 124: Figure 5-4. Superconducting 16x16 c
Page 125 and 126: 06 The design of secondary packagin
Page 127 and 128: For this study, the readiness of th
Page 129 and 130: 6.1.3 MULTI-CHIP MODULES AND BOARDS
Page 131 and 132: TABLE 6-2. MCM FABRICATION TOOLS AN
Page 133 and 134: 6.2.3. 3-D PACKAGING - ISSUES AND C
Page 135 and 136: Several companies have demonstrated
Page 137 and 138: In selecting the cooling approach f
Page 139 and 140: Another issue is the cost of the re
Page 141 and 142: Some of the thermal and electrical
Page 143 and 144: Optical interconnects may require t
Page 145 and 146: 6.6.4 SYSTEM INTEGRITY AND TESTING
Page 147 and 148: Appendix A
Page 149 and 150: ■ ■ ■ ■ Construct a detaile
Page 151 and 152: Appendix B
Page 153 and 154: GOVERNMENT George Cotter Director f
Page 155 and 156: Appendix C
Page 157 and 158: TERMS/DEFINITIONS IHEC LLNL JJ JPL
Page 159 and 160: Appendix D
Page 161 and 162: The time-dependent behavior of this
Page 163: RSFQ electronics is faster and diss
Page 167 and 168: Appendix E
Page 169 and 170: The report further identified four
Page 171 and 172: Analog high temperature superconduc
Page 173 and 174: Appendix F
Page 175 and 176: Only one significant effort to arch
Page 177 and 178: Execution Models Organizing hardwar
Page 179 and 180: Development Issues and Approaches T
Page 181 and 182: Appendix G
Page 183 and 184: The two-junction comparator, the ba
Page 185 and 186: Bias Currents A major cause of degr
Page 187 and 188: Power and bias current Power is dis
Page 189 and 190: Appendix H
Page 191 and 192: SMT MRAM Another direct selection s
Page 193 and 194: Speed and Density The first planned
Page 195 and 196: 120 0.10 100 Write I (mA) 0.08 0.06
Page 197 and 198: Appendix I
Page 199 and 200: Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Table 5 Reactive Ion Etch Parameter
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: shorts in the first wiring layer we
Page 209 and 210: B. Yield Yield measurements are an
Page 211 and 212: RSFQ logic will eventually find wid
Page 213 and 214: [47] B. Bumble, H. G. LeDuc, J. A.
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Appendix J
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Fig. 2. The Schematic View describe
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Fig. 4. The VHDL View captures the
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Fig. 6. LMeter is specialized softw
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Fig. 8. Layout-versus-Schematic ver
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Appendix K
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1. CURRENT STATUS OF OPTICAL INTERC
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1.2. CURRENT OPTICAL INTERCONNECT R
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If technology, power, or cost limit
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3.4 COARSE VS. DENSE WAVE DIVISION
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3.5 DEVELOPMENTS FOR LOW TEMPERATUR
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5. ROADMAP The roadmap below shows
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Appendix L
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The bandwidth, chip density and int
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While using short flex cables is th
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We must note that the reparability
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Intermediate Temperature stage Disp
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Small Cryocoolers Among commercial
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Although cooling of the 4 K circuit
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Supplying DC current to all of the
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These properties enable the possibi
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