Superconducting Technology Assessment - nitrd

2.5 MICROPROCESSORS – CONCLUSIONS AND GOALS
In the opinion of the panel, it will be possible to find and demonstrate viable solutions for these architectural and
design challenges in the context of a practical RSFQ processor to be demonstrated by 2010.
In the 2005-2010 roadmap, the processor design goals will be the following:
TABLE 2-5. PROCESSOR DESIGN GOALS 2005-010
1. Find Architectural Solutions for 50-100 GHz Superconductor Processors
– Identify performance bottlenecks for superconductor processors at the microarchitectural level.
– Develop a viable architecture capable of avoiding and/or tolerating expected pipeline
and memory latencies.
2. Design a 50 GHz 32-bit Multi-chip Processor with Local Memory
with the Following Characteristics:
– Clock frequency: 50 GHz 1 .
– Performance (peak): 50 GOPS (integer), 100-200 GFLOPS (single precision floating-point).
– Logic complexity: ~ 1M gates.
– Local memory capacity (total): 128 KByte (multiple chips/banks).
– Local memory bandwidth (peak): 200-400 GB/sec (~2 Bytes per flop), Packaging: one MCM.
3. Demonstrate Functionality and Evaluate Performance
of the 50 GHz 32-bit Processor with Local Memory
– Develop a detailed simulation model and write a set of test and benchmark programs.
– Evaluate functionality and performance of the 50 GHz 32-bit processor with local memory
on a set of test and benchmark programs.
The architecture and microarchitecture design tasks are a pacing item. They should be initiated as soon as possible
in order to develop efficient solutions, and provide first logical specifications of the processor chips for circuit
designers as soon as the RSFQ fabrication facility becomes operational.
1
“As mentioned earlier in this Chapter 2, a 50 GHz superconductor processor may employ multiple clock domains potentially with different
local clock frequencies, which could be higher or lower than the 50 GHz clock target for data processing units.“
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