Superconducting Technology Assessment - nitrd

Figure 3.3-1. ADC chip containing about 6,000 JJs was developed
by HYPRES. This integration scale can be achieved by experts in the
field using design rule checking (DRC) CAD verification.
Figure 3.3-2. A bit-serial superconductor microprocessor
featuring 6,300 JJs, 7 instructions, and a 16 GHz clock. The circuit
was developed and tested by an independent consortium of
Japanese universities.
Readiness
The IC design software developed by Stony Brook University and the University of Rochester was integrated into a
single suite at Northrop Grumman. The readiness of U.S.-based design methodology and CAD tools is described
below using the Northrop Grumman capability as an example. While built upon the academic projects, it also leverages
the methodology and software that serves the commercial semiconductor ASIC world.
A significant challenge for fabrication at or below the 0.25-micron node is the development of inductance extraction
software that is accurate for smaller features. Cadence supports extraction of device parameters from the physical
layout. However, extraction of inductance values is not well-supported. New software should use 3-dimensional
modeling of magnetic fields to accurately predict the inductance of sub micron lines.
Hardware Description Language (HDL) models need to contain the right information, such as gate delay as a function
of the parasitic inductive load associated with the physical wiring between gates. Standards for gate models exist,
such as standard delay format in which gate delay is given in terms of nominal, typical high, and typical low
values of physical parameters.
VHDL has been used in the design of such complex multichip superconductive digital systems such as Northrop
Grumman’s programmable bandpass A/D converter that combined mixed signal, digital signal processing, and
memory elements. The same schematic used to design the circuit in VHDL can be used for layout-versus-schematic
(LVS) verification.
By combining process control monitor and visual inspection data to characterize each die on the foundry side with
CAD verification on the designers side, first-pass success had become routine for chips of up to a few-thousand
JJs fabricated in the Northrop Grumman foundry.
68