Superconducting Technology Assessment - nitrd

Fig. 8. Layout-versus-Schematic verification on the chip level for a large chip. LVS software checks the mask drawing against the circuit schematic,
to identify errors such as open circuits, missing pieces, and extra components not included in the design simulation.
The same schematic that is used to design the circuit in VHDL can be used for layout-versus-schematic (LVS)
verification. This is done all the way up to the chip level. Figure 8 shows an example chip containing a few thousand
JJs that was verified in this way. Of course, design rule checking (DRC) is also performed on the entire chip.
First-pass success has become routine for chips of up to a few-thousand JJs manufactured in the Northrop
Grumman foundry. This was achieved by the union of design verification and, on the foundry side, reduction of
process control monitor and visual inspection data to characterize each die. Figure 9 is a gallery of chips, designed
variously in 4kA/cm 2 Nb, 8kA cm 2 Nb, and 1kA cm 2 NbN foundry technologies that achieved first pass success. For
these designs, functionality was achieved on the first die that was tested.
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