Superconducting Technology Assessment - nitrd

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MULTI-CHIP MODULES AND BOARDS In order to accommodate thousands of processor and other support chips for a SCE-based petaflops scale Supercomputer, multi-chip packaging that minimizes interconnects latency (i.e., Time of flight (TOF) and minimizes the total area and volume is needed. A well designed hierarchy of secondary packaging starting from SCE and memory chips and including multi-chip modules (very dense substrates supporting these chips) and printed circuit boards housing MCMs is needed. The secondary packaging problem for large-scale SCE systems was investigated in previous programs such as HTMT 1 . A typical approach is shown in Figure 1. This package occupies about 1 m 3 with a power density of 1 kW at 4 K. Chips are mounted on 512 multi-chip modules (MCM) that allow a chip-to-chip bandwidth of 32 Gbps per channel. Bisectional bandwidth into and out of the cryostat is 32 Pbps. PCBs MCMs Intra- MCM cables I/Os Figure 1. Packaging concept for HTMT SCP, showing 512 fully integrated multi-chip modules (MCMs) connected to 160 octagonal printed circuit boards (PCBs). The MCMs, stacked four high in blocks of 16, are connected to each other vertically with the use of short cables, and to room temperature electronics with flexible ribbon cables (I/Os). The drawing has one set of the eight MCM stacks missing, and only shows one of the eight sets of I/O cable. Each MCM, up to 20 cm on a side, has up to 50 SCE chips and 8 processor units. Flip-chip bonding is used to attach the chips to the MCM providing high interconnect density (2,000-5,000 pinouts per chip), multi-Gbps data rates, automated assembly, and reworkability. The cutoff frequency of channels between chips is in the THz regime. The vertical MCMs are edge-mounted to 160 horizontal multi-layer printed circuit boards (PCB) which allows for MCM-to-MCM connections. Adjacent MCMs are connected to each other along their top and bottom edges with flexible ribbon cable. These cables consist of lithographically defined signal lines on a substrate of polyimide film in a stripline configuration, which have been demonstrated in a cryogenic test station at data rates up to 3 Gbps. A cryogenic network (CNET) allows any processor unit to communicate with any other with less than 20 ns latency. 1 HTMT Program Phase III Final Report, 2002 227
The bandwidth, chip density and interconnect distance requirements place multi-chip modules (MCM) as the leading candidate technology for large SCE-based systems. The MCM requirements include: ■ ■ ■ Use of niobium wiring for the dielectric portion of the MCM (MCM-D). A combination ceramic and dielectric MCM (MCM C+D) technology. Low impedance transmission lines. The MCM is projected can hold 50 chips on a 20 cm X 20 cm substrate and pass data at 32 Gbps (Figure 2). It will have multiple wiring layers (up to nine superconductor wires), separated by ground planes and will need to accommodate different impedance wiring. To date, 20 SCE chips have been attached to an MCM of this type, each chip with 1,360 bumps. Figure 2. A multi-chip module with SCE chips(left, NGST‘s Switch chip MCM with amplifier chip; center, NGST’s MCM; right, HYPRES’ MCM). Although MCMs with SCE chips are feasible, the signal interface and data links impose further challenges. The large number of signal channels and high channel densities is difficult to achieve for two reasons: 1. The signals pass from the chips into the MCM layers within the area constraints of the pad geometry (maximum connection density for this process is dominated by via diameter and via capture pad area). 2. The MCM must transport signals laterally between chips and to peripheral connectors (maximum density for lateral signal transmission is determined by the wiring pitch and the number of layers). 1) Chip-to-MCM I/O: The issues for the die attach are the pin-out density (2 k to 5 k signal pads per chip), and the inductance (< 10 pH) and bandwidth requirements (>50 Gbps). The leading candidate for the chip-to-MCM attach is flip-chip bonding utilizing solder reflow connections. This attach method allows for both high interconnect densities as well as the low-inductance connections required for 32 Gbps data transmission. Figure 3 gives interconnect inductance as a function of bond length or height for different types of interconnects. Other candidate technologies typically suffer from either insufficient interconnect densities or relatively large inductances which limit data rates to less than 10 Gbps. A data rate of 32 Gbps between chips appears feasible using appropriate superconductor driver and receiver circuits. Bandwidth is limited by a L/R time constant, where L is the inductance of the chip-to-MCM bump and R is the impedance of the microstrip wiring. For reasonable values of L (3-10 pH) and R (10-20 Ω), the cutoff frequency is in the THz regime. 228
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SUPERCONDUCTING TECHNOLOGY ASSESSME
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Summary of Findings The STA conclud
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CHAPTER 02: ARCHITECTURAL CONSIDERA
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CHAPTER 06: SYSTEM INTEGRATION 6.1
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INDEX OF FIGURES CHAPTER 01: INTROD
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APPENDIX G: ISSUES AFFECTING RSFQ C
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CONTENTS OF CD EXECUTIVE SUMMARY CH
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LIMITATIONS OF CURRENT TECHNOLOGY C
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State of the Industry Today, expert
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01 This document presents the resul
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1.2 LIMITATIONS OF CONVENTIONAL TEC
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1.3.2 RSFQ ATTRIBUTES Important att
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The end point of this roadmap defin
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CRYOGENIC ENVIRONMENT High-speed ne
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■ ■ Chalmers University in Swed
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Random Access Memory Options Random
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Compact Package Feasible Thousands
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The major issue to be addressed wil
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02 No radical execution paradigm sh
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The key challenges at the processor
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2.2 MICROPROCESSORS - CURRENT STATU
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2.2.3 CORE1 BIT-SERIAL MICROPROCESS
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Potential Problems The initial vers
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The microarchitecture of supercondu
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2.5 MICROPROCESSORS - CONCLUSIONS A
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2.7 MICROPROCESSORS - FUNDING In th
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SUPERCONDUCTIVE RSFQ PROCESSOR AND
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3.1 RSFQ PROCESSORS The panel devel
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TABLE 3.1-1. PUBLISHED SUPERCONDUCT
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S G G Chip-side microstrip S Carrie
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3.1.3 RSFQ PROCESSORS - ROADMAP The
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3.1.5 RSFQ PROCESSORS - ISSUES AND
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Since these memory concepts are so
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Simulations show that the input int
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SFQ RAM Status The results of five
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Investment for SFQ Memory The inves
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4MB MRAM BIT CELL: 1 MTJ & 1 TRANSL
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The roadmap identifies early analyt
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MRAM Major Issues and Concerns Mate
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3.3 CAD TOOLS AND DESIGN METHODOLOG
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Issues and Concerns Present simulat
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Investment The investment estimated
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04 By 2010 production capability fo
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Table 4-1 summarizes the roadmap fo
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4.1 SCE IC CHIP MANUFACTURING - SCO
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Significant activity in the area of
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4.3 SCE CHIP FABRICATION FOR HEC -
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The superconductive IC chip fabrica
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Table 4-6 shows how gate speed depe
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Parameter spreads in superconductiv
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TABLE 4-9. SCALING REQUIREMENTS FOR
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ELEMENT 2006 2007 2008 2009 2010 Pi
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A potential savings of ~40% in the
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05 Packaging and chip-to-chip inter
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TABLE 5-1. I/O TECHNOLOGIES FOR PET
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For further discussions of the opti
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5.1.3 OPTICAL INTERCONNECT TECHNOLO
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In this case, an optical receiver w
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Examples of what has been achieved
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5.3.4 OUTPUT: 4 K RSFQ TO ROOM TEMP
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Figure 5-4. Superconducting 16x16 c
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06 The design of secondary packagin
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For this study, the readiness of th
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6.1.3 MULTI-CHIP MODULES AND BOARDS
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TABLE 6-2. MCM FABRICATION TOOLS AN
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6.2.3. 3-D PACKAGING - ISSUES AND C
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Several companies have demonstrated
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In selecting the cooling approach f
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Another issue is the cost of the re
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Some of the thermal and electrical
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Optical interconnects may require t
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6.6.4 SYSTEM INTEGRITY AND TESTING
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Appendix A
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■ ■ ■ ■ Construct a detaile
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Appendix B
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GOVERNMENT George Cotter Director f
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Appendix C
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TERMS/DEFINITIONS IHEC LLNL JJ JPL
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Appendix D
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The time-dependent behavior of this
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RSFQ electronics is faster and diss
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Similar to CMOS, the irreducible po
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Appendix E
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The report further identified four
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Analog high temperature superconduc
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Appendix F
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Only one significant effort to arch
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Execution Models Organizing hardwar
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Development Issues and Approaches T
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Appendix G
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The two-junction comparator, the ba
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Bias Currents A major cause of degr
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Power and bias current Power is dis
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Page 191 and 192: SMT MRAM Another direct selection s
Page 193 and 194: Speed and Density The first planned
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Page 197 and 198: Appendix I
Page 199 and 200: Table 1 Representative Nb and NbN-B
Page 201 and 202: ground plane may be located either
Page 203 and 204: Table 5 Reactive Ion Etch Parameter
Page 205 and 206: Table 6 Junction Array Summary of T
Page 207 and 208: shorts in the first wiring layer we
Page 209 and 210: B. Yield Yield measurements are an
Page 211 and 212: RSFQ logic will eventually find wid
Page 213 and 214: [47] B. Bumble, H. G. LeDuc, J. A.
Page 215 and 216: Appendix J
Page 217 and 218: Fig. 2. The Schematic View describe
Page 219 and 220: Fig. 4. The VHDL View captures the
Page 221 and 222: Fig. 6. LMeter is specialized softw
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Page 225 and 226: Appendix K
Page 227 and 228: 1. CURRENT STATUS OF OPTICAL INTERC
Page 229 and 230: 1.2. CURRENT OPTICAL INTERCONNECT R
Page 231 and 232: If technology, power, or cost limit
Page 233 and 234: 3.4 COARSE VS. DENSE WAVE DIVISION
Page 235 and 236: 3.5 DEVELOPMENTS FOR LOW TEMPERATUR
Page 237 and 238: 5. ROADMAP The roadmap below shows
Page 239: Appendix L
Page 243 and 244: While using short flex cables is th
Page 245 and 246: We must note that the reparability
Page 247 and 248: Intermediate Temperature stage Disp
Page 249 and 250: Small Cryocoolers Among commercial
Page 251 and 252: Although cooling of the 4 K circuit
Page 253 and 254: Supplying DC current to all of the
Page 255 and 256: These properties enable the possibi
Page 257: For additional copies, please conta
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